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公开(公告)号：US08737000B2
公开(公告)日：2014-05-27
申请号：US13550308
申请日：2012-07-16
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B5/02 , G11B5/746 , G11B20/10305 , G11B20/10481
摘要： Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.
摘要翻译： 描述用于确定通信路径的定时等待时间的方法。 一些实施例涉及用于测试定时等待时间的方法。 信号在第一数据路径上被驱动，并通过环路元件通过第二数据路径返回。 使用在第二数据路径上返回的信号来测试包括第一数据路径和第二数据路径的通信路径的至少一部分的定时等待时间。 在测试时间延迟期间，将第二数据路径的增益调整为测试值。
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公开(公告)号：US20140016221A1
公开(公告)日：2014-01-16
申请号：US13550296
申请日：2012-07-16
摘要： Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.
摘要翻译： 包括用于在存储装置的写入模式期间确定即将到来的读取区域的存在以及响应于感测的读取区域启动存储设备的读取（RWW）模式的系统和方法。 启动RWW模式包括预热读取器电路，响应于写入操作的结束产生信号，以及响应于产生的信号激活读取器偏置电流。
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公开(公告)号：US08861115B2
公开(公告)日：2014-10-14
申请号：US13550296
申请日：2012-07-16
IPC分类号： G11B5/09
摘要： Systems and methods are included for determining a presence of an upcoming reading field during a write mode of a storage device, and initiating a read-while write (RWW) mode of the storage device in response to the sensed reading field. Initiating the RWW mode comprises warming up the reader circuitry, generating a signal in response to an end to the write operation, and activating reader bias current in response to the generated signal.
摘要翻译： 包括用于在存储装置的写入模式期间确定即将到来的读取区域的存在以及响应于感测的读取区域启动存储设备的读取（RWW）模式的系统和方法。 启动RWW模式包括预热读取器电路，响应于写入操作的结束产生信号，以及响应于产生的信号激活读取器偏置电流。
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公开(公告)号：US20140016222A1
公开(公告)日：2014-01-16
申请号：US13550308
申请日：2012-07-16
CPC分类号： G11B5/09 , G11B5/02 , G11B5/746 , G11B20/10305 , G11B20/10481
摘要： Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.
摘要翻译： 描述用于确定通信路径的定时等待时间的方法。 一些实施例涉及用于测试定时等待时间的方法。 信号在第一数据路径上被驱动，并通过环路元件通过第二数据路径返回。 使用在第二数据路径上返回的信号来测试包括第一数据路径和第二数据路径的通信路径的至少一部分的定时等待时间。 在测试时间延迟期间，将第二数据路径的增益调整为测试值。
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公开(公告)号：US08582226B2
公开(公告)日：2013-11-12
申请号：US13421547
申请日：2012-03-15
IPC分类号： G11B5/02
摘要： Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory.
摘要翻译： 写延迟稳定的装置和方法。 写驱动器适于输出双极写入电流以将数据写入存储器。 预处理电路适于通过写入驱动器输出第一和第二热预处理电流，以便在将数据写入存储器之前将与写入驱动器相关联的写入延迟稳定在稳定状态。
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公开(公告)号：US08402205B2
公开(公告)日：2013-03-19
申请号：US12726486
申请日：2010-03-18
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7207
摘要： Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group.
摘要翻译： 用于管理与数据存储阵列相关联的元数据的方法和装置。 根据各种实施例，一组用户数据块被存储到阵列的所选物理地址处的存储器单元。 使用多层元数据方案来生成描述用户数据块的选定物理地址的元数据。 多层元数据方案提供适用于N个用户数据块组的上层元数据格式，以及适用于M小于N的M个用户数据块组的较低层元数据格式。所生成的元数据根据 相对于组中的用户数据块的总数，选择的上层或下层元数据格式之一。
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公开(公告)号：US20100202079A1
公开(公告)日：2010-08-12
申请号：US12475001
申请日：2009-05-29
申请人： Bruce Douglas Buch , Mathew P. Vea
发明人： Bruce Douglas Buch , Mathew P. Vea
IPC分类号： G11B5/09
CPC分类号： G11B5/59655 , B82Y10/00 , G11B5/743 , G11B5/746 , G11B20/10009 , G11B20/10222 , G11B20/10425 , G11B20/10481 , G11B20/14 , G11B2005/0005 , G11B2020/1275 , G11B2220/2516
摘要： A technique is described for write synchronization phase calibration for storage media (e.g., bit patterned media). In one embodiment, a calibration write clock signal may be generated at a frequency offset from a nominal dot frequency of a bit patterned storage media. A periodic signal that was written to the media synchronous to the calibration write clock signal may then be read and mixed with a reference periodic signal at the nominal dot frequency to obtain a difference signal. This difference signal may be demodulated to determine a phase correction for write synchronization to the media.
摘要翻译： 描述了用于存储介质（例如，位图形介质）的写入同步相位校准的技术。 在一个实施例中，校准写时钟信号可以以与位图形存储介质的标称点频率偏移的频率产生。 然后可以将与校准写入时钟信号同步的写入媒体的周期性信号读取并以标称点频率与参考周期信号混合，以获得差分信号。 该差分信号可以被解调以确定用于与介质的写入同步的相位校正。
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公开(公告)号：US20130124591A1
公开(公告)日：2013-05-16
申请号：US13297009
申请日：2011-11-15
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.
摘要翻译： 使用与电路硬件相关的熵特性生成随机数。 与一种方法一致，使用开关电压调节器电路来产生随机数。 产生响应于开关稳压器电路的开关状态的数据。 然后从生成的数据生成多位随机数。
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9.发明授权公开(公告)号：US07969676B2
公开(公告)日：2011-06-28
申请号：US12267305
申请日：2008-11-07
IPC分类号： G11B27/36
CPC分类号： G11B5/59616 , B82Y10/00 , G11B5/09 , G11B5/743
摘要： Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium.
摘要翻译： 描述技术来提供用于数据存储介质上的操作的媒体参考定时。 特别地，锁相环（PLL）同步字段可以散布在介质的数据字段内，并且可以被读取以获得定时测量。 说明性地在介质上以预定的间隔预先记录PLL场，并且在PLL场之间具有固定数量的位图案化介质的点。 可以基于读取的PLL字段来控制写时钟的相位和频率，以将来自PLL场的定时测量值转换为相位和频率校正，以将写入时钟同步到数据存储介质。
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公开(公告)号：US20100118433A1
公开(公告)日：2010-05-13
申请号：US12266677
申请日：2008-11-07
申请人： Bruce Douglas Buch
发明人： Bruce Douglas Buch
IPC分类号： G11B21/02
摘要： A write precompensation system comprises a write precompensation processor that calculates time shift information for the timing of individual write current transitions at a write head to coincide with a media pattern under the write head and a write precompensation controller that shifts the individual write current transitions in accordance with the time shift information.
摘要翻译： 一种写入预补偿系统，包括一个写入预补偿处理器，用于计算在写入头处的各个写入电流转换的定时的时间偏移信息，以与写入头下面的介质模式一致;以及写入预补偿控制器， 与时间偏移信息。
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