公开(公告)号：US07757027B2

公开(公告)日：2010-07-13

申请号：US12213470

申请日：2008-06-19

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F13/00

CPC分类号： G06F13/4221

摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

公开(公告)号：US07254658B2

公开(公告)日：2007-08-07

申请号：US10862872

申请日：2004-06-08

申请人： Antony John Harris ,  Bruce James Mathewson

发明人： Antony John Harris ,  Bruce James Mathewson

IPC分类号： G06F13/00

CPC分类号： G06F13/423

摘要： A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

摘要翻译： 总线主机2,4将写入事务发送到总线从机8，总线从机8包括单独的写入地址AW和写入数据WD。 写事务标识符AWID，WID与这些写入地址和写入数据相关联。 总线从站可以接受多个写入地址，以便可以对同一总线从站进行共同的写入事务。 总线从站使用写事务标识符将共同待处理写入事务的交错写入数据与其写入地址相关联。

公开(公告)号：US07925840B2

公开(公告)日：2011-04-12

申请号：US12230880

申请日：2008-09-05

申请人： Antony John Harris ,  Bruce James Mathewson ,  Christopher William Laycock

发明人： Antony John Harris ,  Bruce James Mathewson ,  Christopher William Laycock

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  Y02D10/13

摘要： The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches. When a snoop process is required, a snoop unit is used to reference the snoop control storage in order to identify, having regard to one or more properties of the access request, the snoop scheme to be employed to perform the snoop process. Such an approach provides a great deal of flexibility with regards to how snoop processes are implemented, in particular allowing different snoop schemes to be used dependent on the properties of the access request in question.

摘要翻译： 本发明提供了一种用于管理窥探操作的数据处理装置和方法。 数据处理装置具有多个处理单元，用于执行需要访问共享存储器中的数据的数据处理操作，其中至少两个处理单元具有与其相关联的高速缓冲存储器，用于存储用于该处理单元访问的数据的子集。 采用基于窥探的高速缓存一致性协议来确保每个处理单元访问的数据是最新的，并且当发出访问请求时，引用高速缓存一致性协议以便确定是否需要侦听进程。 提供了侦听控制存储器，其定义了多个侦听方案，每个侦听方案定义了要执行的一系列侦听阶段以实现侦听进程，并且每个侦听阶段需要在单个缓存或多个缓存上执行侦听操作 。 当需要窥探过程时，窥探单元用于引用窥探控制存储器，以便在考虑到访问请求的一个或多个属性的情况下识别要用于执行窥探处理的窥探方案。 这种方法提供了关于如何实现侦听进程的大量灵活性，特别是允许根据所讨论的访问请求的属性使用不同的侦听方案。

公开(公告)号：US07213092B2

公开(公告)日：2007-05-01

申请号：US10862900

申请日：2004-06-08

申请人： Antony John Harris ,  Bruce James Mathewson

发明人： Antony John Harris ,  Bruce James Mathewson

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G06F13/4243

摘要： An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read address channel. The provision of a dedicated write response channel frees the read data channel to be more efficiently used for the transfer of read data. Transactions may be burst mode transactions with a single write response corresponding to the write transaction as a whole.

摘要翻译： 集成电路2具有通过多通道通信总线通信的多个总线主机4,6和多个总线从站8,10,12。 提供单独的写数据通道，读数据通道和写响应通道，以及单独的写地址通道和读地址通道。 提供专用写入响应信道释放读取数据信道以更有效地用于读取数据的传送。 事务可以是具有与整个写入事务相对应的单个写入响应的突发模式事务。

公开(公告)号：US08589631B2

公开(公告)日：2013-11-19

申请号：US13137780

申请日：2011-09-12

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

IPC分类号： G06F12/00

CPC分类号： G06F12/0833 ,  Y02D10/13

摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

摘要翻译： 互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。 至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。 所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。 互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。

公开(公告)号：US20120079211A1

公开(公告)日：2012-03-29

申请号：US13137780

申请日：2011-09-12

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

IPC分类号： G06F12/08

CPC分类号： G06F12/0833 ,  Y02D10/13

摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

摘要翻译： 互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。 至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。 所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。 互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。

公开(公告)号：US08045573B2

公开(公告)日：2011-10-25

申请号：US12310012

申请日：2006-08-16

申请人： Bruce James Mathewson ,  Antony John Harris

发明人： Bruce James Mathewson ,  Antony John Harris

IPC分类号： H04L12/56 ,  H04J1/16

CPC分类号： G06F15/7825 ,  H04L49/102 ,  H04L49/205 ,  H04L49/25 ,  H04L49/602

摘要： An on-chip integrated circuit interconnect 16 uses a serialization technique to divide a transaction to be transmitted into a sequence of transmission packets which are serially transmitted over a narrower connection. The order in which bits of the transaction are allocated to transmission packets is selected such that higher priority bits required by a receiving slave device in order that it can commence processing the transaction are sent first. This reduces the latency of the system.

摘要翻译： 片上集成电路互连16使用串行化技术将要发送的事务划分成通过较窄连接串行发送的传输分组序列。 选择将事务的比特分配给传输分组的顺序，使得首先发送接收从设备为了开始处理事务而需要的较高优先级位。 这减少了系统的延迟。

公开(公告)号：US20100064108A1

公开(公告)日：2010-03-11

申请号：US12230880

申请日：2008-09-05

申请人： Antony John Harris ,  Bruce James Mathewson ,  Christopher William Laycock

发明人： Antony John Harris ,  Bruce James Mathewson ,  Christopher William Laycock

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  Y02D10/13

摘要： The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches. When a snoop process is required, a snoop unit is used to reference the snoop control storage in order to identify, having regard to one or more properties of the access request, the snoop scheme to be employed to perform the snoop process. Such an approach provides a great deal of flexibility with regards to how snoop processes are implemented, in particular allowing different snoop schemes to be used dependent on the properties of the access request in question.

摘要翻译： 本发明提供了一种用于管理窥探操作的数据处理装置和方法。 数据处理装置具有多个处理单元，用于执行需要访问共享存储器中的数据的数据处理操作，其中至少两个处理单元具有与其相关联的高速缓冲存储器，用于存储用于该处理单元访问的数据的子集。 采用基于窥探的高速缓存一致性协议来确保每个处理单元访问的数据是最新的，并且当发出访问请求时，引用高速缓存一致性协议以便确定是否需要侦听进程。 提供了侦听控制存储器，其定义了多个侦听方案，每个侦听方案定义了要执行的一系列侦听阶段以实现侦听进程，并且每个侦听阶段需要在单个缓存或多个缓存上执行侦听操作 。 当需要窥探过程时，窥探单元用于引用窥探控制存储器，以便在考虑到访问请求的一个或多个属性的情况下识别要用于执行窥探处理的窥探方案。 这种方法提供了关于如何实现侦听进程的大量灵活性，特别是允许根据所讨论的访问请求的属性使用不同的侦听方案。

公开(公告)号：US07213095B2

公开(公告)日：2007-05-01

申请号：US10862884

申请日：2004-06-08

申请人： Peter Guy Middleton ,  David John Gwilt ,  Ian Victor Devereux ,  Bruce James Mathewson ,  Antony John Harris ,  Richard Roy Grisenthwaite

发明人： Peter Guy Middleton ,  David John Gwilt ,  Ian Victor Devereux ,  Bruce James Mathewson ,  Antony John Harris ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/36

CPC分类号： G06F13/1631

摘要： A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

摘要翻译： 数据处理系统具有总线，该总线具有分开的写通道W和读通道R，通过该通道进行总线交易。 总线事务缓冲器34设置在总线结构内以缓冲写入请求，特别是为了减轻与相对较慢的总线从站相关联的问题。 总线事务缓冲器34响应于与写入请求相关联的存储器地址和通过它们的读取请求，以将它们识别到相同存储器地址或者在预定范围内的存储器地址，以便确保那些 交易，读取以遵循写入，或者在写入缓冲写入数据值之后满足读取，然后刷新读取请求，使其不到达其最终目的地。

公开(公告)号：US20090323685A1

公开(公告)日：2009-12-31

申请号：US12310012

申请日：2006-08-16

申请人： Bruce James Mathewson ,  Antony John Harris

发明人： Bruce James Mathewson ,  Antony John Harris

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： G06F15/7825 ,  H04L49/102 ,  H04L49/205 ,  H04L49/25 ,  H04L49/602

摘要： An on-chip integrated circuit interconnect 16 uses a serialization technique to divide a transaction to be transmitted into a sequence of transmission packets which are serially transmitted over a narrower connection. The order in which bits of the transaction are allocated to transmission packets is selected such that higher priority bits required by a receiving slave device in order that it can commence processing the transaction are sent first. This reduces the latency of the system.

摘要翻译： 片上集成电路互连16使用串行化技术将要发送的事务划分成通过较窄连接串行发送的传输分组序列。 选择将事务的比特分配给传输分组的顺序，使得首先发送接收从设备为了开始处理事务而需要的较高优先级位。 这减少了系统的延迟。