公开(公告)号：US07213095B2

公开(公告)日：2007-05-01

申请号：US10862884

申请日：2004-06-08

申请人： Peter Guy Middleton ,  David John Gwilt ,  Ian Victor Devereux ,  Bruce James Mathewson ,  Antony John Harris ,  Richard Roy Grisenthwaite

发明人： Peter Guy Middleton ,  David John Gwilt ,  Ian Victor Devereux ,  Bruce James Mathewson ,  Antony John Harris ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/36

CPC分类号： G06F13/1631

摘要： A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

摘要翻译： 数据处理系统具有总线，该总线具有分开的写通道W和读通道R，通过该通道进行总线交易。 总线事务缓冲器34设置在总线结构内以缓冲写入请求，特别是为了减轻与相对较慢的总线从站相关联的问题。 总线事务缓冲器34响应于与写入请求相关联的存储器地址和通过它们的读取请求，以将它们识别到相同存储器地址或者在预定范围内的存储器地址，以便确保那些 交易，读取以遵循写入，或者在写入缓冲写入数据值之后满足读取，然后刷新读取请求，使其不到达其最终目的地。

公开(公告)号：US07024543B2

公开(公告)日：2006-04-04

申请号：US10242671

申请日：2002-09-13

申请人： Richard Roy Grisenthwaite ,  Ian Victor Devereux

发明人： Richard Roy Grisenthwaite ,  Ian Victor Devereux

IPC分类号： G06F9/38 ,  G06F9/52

CPC分类号： G06F9/3865 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885

摘要： The present invention provides an apparatus and method for synchronizing a first pipeline and a second pipeline of a processor arranged to execute a sequence of instructions. The processor is arranged to route an instruction in the sequence through either the first or the second pipeline dependent on predetermined criteria, each pipeline having a plurality of pipeline stages including a retirement stage. Counter logic is provided for maintaining a first counter relating to the first pipeline and a second counter relating to the second pipeline. For each instruction in the first pipeline a determination is made as to when that instruction reaches a point within the first pipeline where an exception status of that instruction is resolved, and the counter logic is arranged to increment the first counter responsive to such determination. The processor is arranged to generate an indication within the second pipeline each time an instruction is routed to the first pipeline, and the counter logic is further arranged to increment the second counter responsive to that indication. Synchronisation logic is then provided which is arranged, when an instruction is in the retirement stage of the second pipeline, to determine with reference to the values of the first and second counters whether that instruction can be retired. If so, the retirement stage is arranged to cause an update of a state of the data processing apparatus dependent on the result of execution of that instruction.

摘要翻译： 本发明提供了一种用于使被配置为执行指令序列的处理器的第一流水线和第二流水线同步的装置和方法。 处理器被布置为依赖于预定标准来通过第一或第二流水线顺序地路由指令，每个流水线具有包括退休阶段的多个流水线阶段。 计数器逻辑被提供用于维持与第一流水线相关的第一计数器和与第二流水线相关的第二计数器。 对于第一流水线中的每个指令，确定何时该指令到达该指令的异常状态的第一流水线内的一个点，并且该计数器逻辑被布置成响应于这种确定来增加第一计数器。 处理器被布置为在每次将指令路由到第一流水线时在第二流水线内产生指示，并且计数器逻辑还被布置为响应于该指示递增第二计数器。 然后提供同步逻辑，当指令处于第二流水线的退休阶段时，其被配置为参考第一和第二计数器的值来确定该指令是否可以退休。 如果是这样，退休阶段被安排为依赖于该指令的执行结果来更新数据处理装置的状态。

公开(公告)号：US06941442B2

公开(公告)日：2005-09-06

申请号：US10210060

申请日：2002-08-02

申请人： Ian Victor Devereux

发明人： Ian Victor Devereux

IPC分类号： G06F12/10 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/126 ,  G06F12/1027

摘要： A translation lookaside buffer mechanism is described incorporating a set associative translation lookaside buffer operating in parallel with a fully associative translation lookaside buffer. Lockdown entries are stored within the fully associative translation lookaside buffer and non-lockdown entries are stored within the set associative translation lookaside buffer. Victim selection for the fully associative translation lookaside buffer 18 is performed using a control register within a coprocessor which is set under operating system software control.

摘要翻译： 描述了翻译后备缓冲机制，其结合了与完全关联翻译后备缓冲器并行操作的集合关联翻译后备缓冲器。 锁定条目存储在完全关联的翻译后备缓冲器中，非锁定条目存储在集合的关联转换后备缓冲器中。 使用在操作系统软件控制下设置的协处理器内的控制寄存器来执行全关联翻译后备缓冲器18的受害者选择。

公开(公告)号：US08803898B2

公开(公告)日：2014-08-12

申请号：US12654385

申请日：2009-12-17

申请人： David Robert Shreiner ,  Ian Victor Devereux ,  Edvard Sørg{dot over (a)}rd ,  Thomas Jeremy Olson

发明人： David Robert Shreiner ,  Ian Victor Devereux ,  Edvard Sørg{dot over (a)}rd ,  Thomas Jeremy Olson

IPC分类号： G06F13/00 ,  G09G5/36 ,  G06T1/00 ,  G06F3/048

CPC分类号： G06T11/40 ,  G09G5/14 ,  G09G5/393 ,  G09G2360/122

摘要： A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

摘要翻译： 使用延迟绘制命令的窗口显示器通过处理写入帧缓冲器30的瓦片22的绘图命令来进行操作，以形成一个或多个新的像素值存储在瓦片存储器40中。表示瓦片内的哪些像素的脏像素数据 存储器是存储新像素值的脏像素，并且还形成了瓦片存储器内的哪些像素不存储新像素值的清洁像素。 根据脏像素数据，存储在瓦片存储器中的新像素值被写入帧缓冲存储器。 对应于瓷砖内存中清洁像素的帧缓冲存储器中存储的像素在未写入时保持不变。

公开(公告)号：US07490221B2

公开(公告)日：2009-02-10

申请号：US10601575

申请日：2003-06-24

申请人： Martin Robert Evans ,  Ian Victor Devereux

发明人： Martin Robert Evans ,  Ian Victor Devereux

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F9/3869 ,  G06F9/3842 ,  G06F9/3881

摘要： The technology described provides a technique for synchronization between pipelines in a data processing apparatus. The data processing apparatus comprises a main processor operable to execute a sequence of instructions, the main processor comprising a first pipeline having a first plurality of pipeline stages, and a coprocessor operable to execute coprocessor instructions in said sequence of instructions. The coprocessor comprises a second pipeline having a second plurality of pipeline stages, and each coprocessor instruction is arranged to be routed through both the first pipeline and the second pipeline. Furthermore, at least one synchronizing queue is provided coupling a predetermined pipeline stage in one of the pipelines with a partner pipeline stage in the other of the pipelines, the predetermined pipeline stage being operable to cause a token to be placed in the synchronizing queue when processing a coprocessor instruction, and the partner pipeline stage being operable to process that coprocessor instruction upon receipt of the token from the synchronizing queue. By this approach, the first and second pipelines are synchronized between the predetermined pipeline stage and the partner pipeline stage, and hence ensures that the pipelines are correctly synchronized for crucial transfers of information without requiring that strict synchronization at all stages is necessary.

摘要翻译： 所描述的技术提供了一种在数据处理设备中的管线之间进行同步的技术。 数据处理装置包括主处理器，可操作以执行指令序列，主处理器包括具有第一多个流水线级的第一流水线，以及可操作以在所述指令序列中执行协处理器指令的协处理器。 协处理器包括具有第二多个流水线级的第二流水线，并且每个协处理器指令被布置成通过第一流水线和第二流水线路由。 此外，提供至少一个同步队列，其将管道中的一个中的预定流水线级与另一管线中的伙伴流水线级联连接，预定流水线级可操作以在处理时将令牌放置在同步队列中 协处理器指令，并且伙伴流水线级可操作以在从同步队列接收到令牌时处理该协处理器指令。 通过这种方法，第一和第二管线在预定的流水线级和伙伴流水线级之间被同步，因此确保管线被正确地同步以用于关键的信息传递，而不需要在所有阶段都需要严格的同步。

公开(公告)号：US06981131B2

公开(公告)日：2005-12-27

申请号：US10233609

申请日：2002-09-04

申请人： Ian Victor Devereux

发明人： Ian Victor Devereux

IPC分类号： G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30094 ,  G06F9/30072 ,  G06F9/3814 ,  G06F9/3867 ,  G06F9/3877

摘要： The present invention provides a data processing apparatus and method for evaluating condition codes comprising a pipelined processor operable to execute a sequence of instructions, a set of condition codes being maintained by the processor, and the state of the condition codes being set by execution of condition code setting instructions in the sequence. The sequence of instructions further includes conditional instructions that are conditionally executed depending on the state of a number of those condition codes, with the pipelined processor comprising a plurality of pipeline stages including a predetermined pipeline stage at which the state of the condition codes are set by the condition code setting instructions. Condition code evaluation logic is associated with the predetermined pipeline stage and is operable, when one of the conditional instructions is in the predetermined pipeline stage, to evaluate the state of the number of the condition codes in order to generate a pass signal indicating whether the conditional instruction is to be executed. Additional condition code evaluation logic is associated with a preceding pipeline stage, and is operable, when one of the conditional instructions is in that preceding pipeline stage, to evaluate the state of the number of the condition codes in order to generate an additional pass signal. Condition code setting instruction determination logic is operable to determine whether there is a condition code setting instruction in either the predetermined pipeline stage or any pipeline stages between said preceding pipeline stage and the predetermined pipeline stage.

摘要翻译： 本发明提供了一种用于评估条件代码的数据处理装置和方法，该数据处理装置和方法包括可操作以执行指令序列的流水线处理器，由处理器维护的一组条件代码，以及通过执行条件设置条件代码的状态 序列中的代码设置说明。 指令序列还包括有条件地执行的条件指令，这些条件指令取决于这些条件代码的数量的状态，流水线处理器包括多个流水线级，包括预定的流水线阶段，状态代码的状态由 条件代码设置指令。 条件代码评估逻辑与预定流水线阶段相关联，并且当条件指令之一处于预定流水线阶段时，可操作以评估条件代码的数量的状态，以便生成指示条件代码的通过信号 指令执行。 附加条件代码评估逻辑与前一流水线阶段相关联，并且当条件指令之一处于前一流水线阶段时，可操作以评估条件代码的数量的状态以便生成附加通过信号。 条件代码设置指令确定逻辑可操作以确定在所述前一流水线级与预定流水线级之间的预定流水线级或任何流水线级是否存在条件代码设置指令。

公开(公告)号：US06691270B2

公开(公告)日：2004-02-10

申请号：US09741897

申请日：2000-12-22

申请人： Conrado Blasco Allué ,  Ian Victor Devereux

发明人： Conrado Blasco Allué ,  Ian Victor Devereux

IPC分类号： G01R3128

CPC分类号： G01R31/318558 ,  G01R31/318555

摘要： The present invention provides a technique for operating an integrated circuit comprising a plurality of circuit elements, with a plurality of serial test scan chains, each being coupled to a different one of the circuit elements. A scan chain selector is responsive to a specified scan chain specifying value to select a corresponding one of the plurality of test scan chains. A scan chain controller is also provided which has a serial interface for receiving signals from outside of the integrated circuit, the scan chain controller comprising an instruction decoder for decoding scan chain controller instructions received from the serial interface. In accordance with the present invention, the decoder is responsive to a first scan chain controller instruction to specify a pre-determined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder. The provision of such a first scan chain controller instruction enables the efficiency of the testing procedure to be improved.

摘要翻译： 本发明提供了一种用于操作包括多个电路元件的集成电路的技术，具有多个串行测试扫描链，每个连接测试扫描链均耦合到不同的电路元件。 扫描链选择器响应于指定的扫描链指定值来选择多个测试扫描链中相应的一个。 还提供了一种扫描链控制器，其具有用于从集成电路外部接收信号的串行接口，扫描链控制器包括用于解码从串行接口接收的扫描链控制器指令的指令解码器。 根据本发明，解码器响应于第一扫描链控制器指令来指定预定的扫描链指定值，以及第二扫描链控制器指令以由解码器解码。 提供这种第一扫描链控制器指令使得能够提高测试过程的效率。

公开(公告)号：US6058439A

公开(公告)日：2000-05-02

申请号：US828501

申请日：1997-03-31

申请人： Ian Victor Devereux

发明人： Ian Victor Devereux

IPC分类号： G06F5/08 ,  G06F13/12 ,  G06F13/00

CPC分类号： G06F5/08 ,  G06F13/122

摘要： A data processing system comprising a first circuit block 6 and a second circuit block 8 linked via an asynchronous first-in-first-out buffer circuit 12 is provided with a burst marker that identifies the first word in a burst transfer or an empty stage. The second circuit block 8 uses the burst marker to identify the last data word in a burst as being that word which immediately precedes such a burst marker.

摘要翻译： 包括经由异步先进先出缓冲器电路12链接的第一电路块6和第二电路块8的数据处理系统被提供有识别突发传送或空白阶段中的第一个字的突发标记。 第二电路块8使用突发标记将突发中的最后数据字识别为紧接在这种突发标记之前的那个字。

公开(公告)号：US20110148892A1

公开(公告)日：2011-06-23

申请号：US12654385

申请日：2009-12-17

申请人： David Robert Shreiner ,  Ian Victor Devereux ,  Edvard Sørgård ,  Thomas Jeremy Olson

发明人： David Robert Shreiner ,  Ian Victor Devereux ,  Edvard Sørgård ,  Thomas Jeremy Olson

IPC分类号： G09G5/36

CPC分类号： G06T11/40 ,  G09G5/14 ,  G09G5/393 ,  G09G2360/122

摘要： A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

摘要翻译： 使用延迟绘制命令的窗口显示器通过处理写入帧缓冲器30的瓦片22的绘图命令来进行操作，以形成一个或多个新的像素值存储在瓦片存储器40中。表示瓦片内的哪些像素的脏像素数据 存储器是存储新像素值的脏像素，并且还形成了瓦片存储器内的哪些像素不存储新像素值的清洁像素。 根据脏像素数据，存储在瓦片存储器中的新像素值被写入帧缓冲存储器。 对应于瓷砖内存中清洁像素的帧缓冲存储器中存储的像素在未写入时保持不变。

公开(公告)号：US07020768B2

公开(公告)日：2006-03-28

申请号：US09792643

申请日：2001-02-26

申请人： Andrew Brookfield Swaine ,  Conrado Blasco Allué ,  Ian Victor Devereux ,  David James Williamson ,  Anthony Neil Berent

发明人： Andrew Brookfield Swaine ,  Conrado Blasco Allué ,  Ian Victor Devereux ,  David James Williamson ,  Anthony Neil Berent

IPC分类号： G06F9/44 ,  G06F11/36

CPC分类号： G06F9/3824 ,  G06F9/3802 ,  G06F11/3466 ,  G06F11/3636

摘要： The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit. The triggering logic comprises at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier. By this approach, the present invention enables a data processing apparatus to be provided with tracing mechanisms and/or debugging mechanisms which can reliably operate even in situations where the sequences of processing instructions from different states of operation occupy overlapping regions in the memory's address space.

摘要翻译： 本发明提供了一种便于调试处理指令序列的装置和方法。 该装置包括用于执行处理指令的处理电路，该处理电路具有多个操作状态，每个操作状态被分配上下文标识符以识别操作状态。 此外，提供逻辑以便于调试由处理电路执行的处理指令的序列。 逻辑包括响应于控制参数的控制逻辑，以执行预定的动作以便于调试，以及触发用于根据从处理电路接收的指示由处理电路执行的处理的数据产生控制参数的逻辑。 触发逻辑包括至少一个上下文标识符比较器，用于将从处理电路接收的数据中提供的上下文标识符与预定上下文标识符进行比较，并产生指示该上下文标识符是否匹配预定上下文标识符的信号。 通过这种方法，本发明使数据处理装置能够提供跟踪机制和/或调试机制，即使在来自不同操作状态的处理指令的序列占据存储器地址空间中的重叠区域的情况下也可以可靠地运行。