公开(公告)号：US08984189B2

公开(公告)日：2015-03-17

申请号：US13461324

申请日：2012-05-01

申请人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

发明人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

IPC分类号： G06F13/12 ,  G11C5/02 ,  H03M13/15

CPC分类号： G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

摘要翻译： 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。

公开(公告)号：US20120284436A1

公开(公告)日：2012-11-08

申请号：US13461324

申请日：2012-05-01

申请人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

发明人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

IPC分类号： G06F13/12

CPC分类号： G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

摘要翻译： 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。

公开(公告)号：US20110161748A1

公开(公告)日：2011-06-30

申请号：US12655590

申请日：2009-12-31

申请人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

发明人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F12/08 ,  G01R31/3177 ,  G06F11/25 ,  H03M13/05 ,  H03M13/15 ,  G11C5/02

CPC分类号： G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

摘要翻译： 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。

公开(公告)号：US08612809B2

公开(公告)日：2013-12-17

申请号：US12655590

申请日：2009-12-31

申请人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

发明人： Bryan Casper ,  Randy Mooney ,  Dave Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F12/08 ,  G01R31/3177 ,  G06F11/25 ,  H03M13/05 ,  H03M13/15 ,  G11C5/02

CPC分类号： G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

公开(公告)号：US20060245485A1

公开(公告)日：2006-11-02

申请号：US11116401

申请日：2005-04-28

申请人： Aaron Martin ,  Pavan Hanumolu ,  Randy Mooney

发明人： Aaron Martin ,  Pavan Hanumolu ,  Randy Mooney

IPC分类号： H03H7/30

CPC分类号： H04L25/03878 ,  H04B3/145

摘要： A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.

摘要翻译： 连续时间均衡器包括：第一跨导电路，用于设定链路中放大信号的增益;以及第二跨导电路，用于在均衡器的传递函数中设置零频率。 零频率基于由第一跨导电路设置的增益来控制在链路中放大的信号的频率范围。

公开(公告)号：US20060226881A1

公开(公告)日：2006-10-12

申请号：US11103527

申请日：2005-04-12

申请人： James Jaussi ,  Randy Mooney

发明人： James Jaussi ,  Randy Mooney

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/085 ,  H03L7/091

摘要： A delay-locked loop (DLL) architecture is provided that includes a voltage controlled delay line, a sample-and-hold circuit and an amplifier circuit. The voltage controlled delay line may have a plurality of buffer stages to provide a first clock signal and a second clock signal. The sample-and-hold circuit may receive signals corresponding to the first clock signal and the second clock signal. The sample-and-hold circuit may provide two sampled signals based on the received signals. Additionally, the amplifier circuit may be coupled to the sample-and-hold circuit and the voltage controlled delay line. The amplifier circuit may provide a control voltage to the buffer stages of the voltage controlled delay line based on the sampled signals received from the sample-and-hold circuit.

摘要翻译： 提供了延迟锁定环（DLL）架构，其包括电压控制延迟线，采样保持电路和放大器电路。 电压控制延迟线可以具有多个缓冲级，以提供第一时钟信号和第二时钟信号。 采样和保持电路可以接收对应于第一时钟信号和第二时钟信号的信号。 采样和保持电路可以基于接收的信号提供两个采样信号。 此外，放大器电路可以耦合到采样保持电路和电压控制的延迟线。 放大器电路可以基于从采样保持电路接收的采样信号向压控延迟线的缓冲级提供控制电压。

公开(公告)号：US20060022728A1

公开(公告)日：2006-02-02

申请号：US10901398

申请日：2004-07-29

申请人： James Jaussi ,  Randy Mooney

发明人： James Jaussi ,  Randy Mooney

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208

摘要： A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitude to a reference signal. The comparator then generates a tail current control signal for the DLL based on a result of the comparison. In one embodiment, the reference signal is indicative of a predetermined tail current value for the DLL, and the tail current control signal adjusts delay of the DLL to equal the predetermined tail current value. Preferably, the tail current control signal maintains the DLL signal output at a substantially constant amplitude in spite of frequency variations and may also be used to set the voltage swing for the DLL.