公开(公告)号：US06807602B1

公开(公告)日：2004-10-19

申请号：US09699877

申请日：2000-10-30

申请人： Bryan Hornung ,  Keith W. Shaw ,  Paul F. Vogel

发明人： Bryan Hornung ,  Keith W. Shaw ,  Paul F. Vogel

IPC分类号： G06F1200

CPC分类号： G06F12/0607

摘要： A data storage system utilizes a plurality of memory systems, at least one processor, and a mapping system. Each of the memory systems has memory and a memory controller for storing and retrieving data. The processor transmits requests for writing data values. These requests include bus addresses. The mapping system maps the bus addresses into memory addresses. The mapping system maps consecutive bus addresses such that the memory addresses mapped from the consecutive bus addresses are interleaved across a plurality of the memory systems. In response to the foregoing requests from the processor, the mapping system identifies checksum system identifiers that identify locations where checksum values to be updated based on the aforementioned data values are stored. The checksum system identifiers preferably identify each of the plurality of mapping systems so that the checksum identifiers and, therefore, the checksum updates that occur based on these checksum system identifiers are interleaved across these memory systems.

摘要翻译： 数据存储系统利用多个存储器系统，至少一个处理器和映射系统。 每个存储器系统具有存储器和用于存储和检索数据的存储器控​​制器。 处理器发送写入数据值的请求。 这些请求包括总线地址。 映射系统将总线地址映射到存储器地址。 映射系统映射连续的总线地址，使得从连续总线地址映射的存储器地址在多个存储器系统之间交错。 响应于来自处理器的上述请求，映射系统识别校验和系统标识符，该校验和系统标识符基于上述数据值被存储来标识要更新的校验和值的位置。 校验和系统标识符优选地识别多个映射系统中的每一个，使得校验和标识符以及因此基于这些校验和系统标识符发生的校验和更新在这些存储器系统之间交错。

公开(公告)号：US06665830B2

公开(公告)日：2003-12-16

申请号：US09773124

申请日：2001-01-31

申请人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

发明人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

IPC分类号： G11C2900

CPC分类号： G06F11/1004

摘要： A system for building checksums efficiently builds a checksum of various data values that are stored in different memory units of a computer system. During the checksum build process, data stores to the memory locations storing the various data values are enabled, thereby enabling the checksum to be built without significantly impacting the performance of the computer system.

公开(公告)号：US06317857B1

公开(公告)日：2001-11-13

申请号：US09759853

申请日：2001-01-12

申请人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

发明人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

IPC分类号： G11C2900

CPC分类号： G06F11/1088 ,  G06F11/1004

摘要： A system for storing and retrieving data utilizes a plurality of memory units having memory locations for storing data values. A checksum of a plurality of the data values in a particular checksum set is maintained in one of the memory locations. One of the plurality of data values can be recovered by combining each of the remaining plurality of data values with the checksum. After retrieving one of the plurality of data values during the data recovery process, steps are taken to ensure that any further attempts to access the location of the retrieved data value do not cause an update to the checksum. Therefore, the locations storing the data values of the checksum set may be accessed (e.g., read from or written to) during the data recovery process without causing errors to the data recovery process.

摘要翻译： 用于存储和检索数据的系统利用具有用于存储数据值的存储器位置的多个存储器单元。 在特定校验和集合中的多个数据值的校验和被保持在存储器位置之一中。 可以通过将剩余的多个数据值中的每一个与校验和组合来恢复多个数据值中的一个。 在数据恢复过程中检索多个数据值中的一个数据值之后，采取步骤以确保进一步尝试访问检索到的数据值的位置不会对校验和进行更新。 因此，可以在数据恢复处理期间存储存储校验和集合的数据值的位置（例如，从其读取或写入），而不会对数据恢复处理造成错误。

公开(公告)号：US07096389B2

公开(公告)日：2006-08-22

申请号：US10236504

申请日：2002-09-06

申请人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

发明人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

IPC分类号： G06F11/00

CPC分类号： G06F11/1048

摘要： A system for moving checksums within memory utilizes a plurality of memory systems and a system manager. A first memory system has a first memory location that is correlated with a checksum indicator. The checksum indicator identifies the memory system that is storing the checksum of the value presently stored at the first location. The system manager dynamically moves the checksum to a destination memory location and updates the checksum indicator such that the checksum indicator identifies the memory system of the destination memory location. While the checksum is being moved, checksum updates may occur to the memory location from which the checksum was moved. Thus, after moving the checksum, the system manager updates the checksum with the value stored at the location from which the checksum was moved. As a result, the checksum stored in the checksum destination location should be sufficiently updated to enable data recovery.

公开(公告)号：US06490668B2

公开(公告)日：2002-12-03

申请号：US09738697

申请日：2000-12-15

申请人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

发明人： Bryan Hornung ,  Gregory S Palmer ,  Paul F. Vogel

IPC分类号： G06F1200

CPC分类号： G06F11/1048

摘要： A system for moving checksums within memory utilizes a plurality of memory systems and a system manager. A first memory system has a first memory location that is correlated with a checksum indicator. The checksum indicator identifies the memory system that is storing the checksum of the value presently stored at the first location. The system manager dynamically moves the checksum to a destination memory location and updates the checksum indicator such that the checksum indicator identifies the memory system of the destination memory location. While the checksum is being moved, checksum updates may occur to the memory location from which the checksum was moved. Thus, after moving the checksum, the system manager updates the checksum with the value stored at the location from which the checksum was moved. As a result, the checksum stored in the checksum destination location should be sufficiently updated to enable data recovery.

摘要翻译： 用于在存储器内移动校验和的系统利用多个存储器系统和系统管理器。 第一存储器系统具有与校验和指示符相关联的第一存储器位置。 校验和指示符标识正在存储当前存储在第一位置的值的校验和的存储器系统。 系统管理员将校验和动态地移动到目的地存储器位置，并更新校验和指示符，使得校验和指示符识别目的地存储器位置的存储器系统。 当校验和被移动时，校验和被移动的内存位置可能会发生校验和更新。 因此，在移动校验和之后，系统管理员使用存储在校验和移动位置的值更新校验和。 结果，存储在校验和目标位置中的校验和应该被充分更新，以使数据恢复。

公开(公告)号：US06948112B2

公开(公告)日：2005-09-20

申请号：US09853955

申请日：2001-05-10

申请人： Bryan Hornung ,  Keith W. Shaw

发明人： Bryan Hornung ,  Keith W. Shaw

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F12/16 ,  G11C29/00 ,  H03M13/00

CPC分类号： G06F11/1469

摘要： A system for performing data error recovery includes a memory unit and a memory controller. The memory unit includes a plurality of memory locations, and the memory controller maintains a checksum in one of the memory locations. At various times, the memory controller receives requests to update the checksum with data values identified by the requests. In response, the memory controller combines the checksum with these data values and stores the foregoing data values into memory. In one embodiment, the memory controller stores the foregoing data values into a plurality of stacks based on which protection domains are associated with the data values. In response to a detection of a data error, the memory controller retrieves a plurality of the stored data values and recovers a previous state of a particular memory location by combining each of the retrieved data values to the checksum.

摘要翻译： 用于执行数据错误恢复的系统包括存储器单元和存储器控制器。 存储器单元包括多个存储器位置，并且存储器控制器在其中一个存储器位置中保持校验和。 在不同时间，存储器控制器接收用请求标识的数据值更新校验和的请求。 作为响应，存储器控制器将校验和与这些数据值组合，并将前述数据值存储到存储器中。 在一个实施例中，存储器控制器基于哪些保护域与数据值相关联将前述数据值存储到多个堆栈中。 响应于数据错误的检测，存储器控制器检索多个存储的数据值，并通过将检索到的每个数据值与校验和组合来恢复特定存储器位置的先​​前状态。

公开(公告)号：US20080147888A1

公开(公告)日：2008-06-19

申请号：US11588903

申请日：2006-10-26

申请人： Chris M. Giles ,  Bryan Hornung ,  Michael J. Phelps ,  Joseph F. Orth

发明人： Chris M. Giles ,  Bryan Hornung ,  Michael J. Phelps ,  Joseph F. Orth

IPC分类号： G06F3/00

CPC分类号： G06F12/06

摘要： One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.

摘要翻译： 在具有不同长度的地址字段的两个或多个地址空间中分配地址的一种示例性方法包括定义地址类型，将值分配给地址字段的高端的第一位以识别第一所述地址类型，在第 地址字段的低端以标识第一所述地址类型的地址，以及在两个或多个地址空间中的第一位和第二位之间插入不同数量的附加位。

公开(公告)号：US07818508B2

公开(公告)日：2010-10-19

申请号：US11741453

申请日：2007-04-27

申请人： Bryan Hornung ,  Erin A. Handgen ,  Gary Gostin ,  Craig Warner

发明人： Bryan Hornung ,  Erin A. Handgen ,  Gary Gostin ,  Craig Warner

IPC分类号： G06F13/00

CPC分类号： G06F12/0607 ,  G06F12/0817 ,  G06F13/1657

摘要： A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.

摘要翻译： 公开了一种计算机系统，诸如处理器代理的相关组件和相关方法。 在至少一个实施例中，计算机系统包括第一核心，包括第一存储器段的至少一个存储器设备和耦合到第一存储器段的第一存储器控制器。 此外，计算机系统包括织物和至少一个处理器代理，至少间接耦合到第一核心和第一存储器段，并且还耦合到织物。 相对于第一存储器段内的第一存储器位置的第一存储器的第一存储器请求通过至少一个处理器代理和结构进行到第一存储器控制器。

公开(公告)号：US07117313B2

公开(公告)日：2006-10-03

申请号：US10803289

申请日：2004-03-18

申请人： Bryan Hornung ,  Bryan Marietta ,  Robert K. King

发明人： Bryan Hornung ,  Bryan Marietta ,  Robert K. King

IPC分类号： G06F12/00

CPC分类号： G06F13/1657

摘要： A SCI controller manages responses and requests between SCI interconnection rings and memory access controllers. The SCI controller includes a request activation queue that stores information about the requests until the SCI rings have the resources to handle the requests. The controller also has a response activation queue that stores information about the responses until the memory access controller is accessible. The queues do not store the request and response packets, but rather store information that is used to construct the request and response packets. The SCI controller also has a contents addressable memory or CAM that checks for an address match between the current requests and responses and previous requests and responses. A table stores more specific information about the previous requests.

摘要翻译： SCI控制器管理SCI互连环和存储器访问控制器之间的响应和请求。 SCI控制器包括一个请求激活队列，用于存储关于请求的信息，直到SCI环有资源来处理请求。 控制器还具有响应激活队列，其存储关于响应的信息，直到存储器访问控制器可访问。 队列不存储请求和响应数据包，而是存储用于构造请求和响应数据包的信息。 SCI控制器还具有内容可寻址存储器或CAM，用于检查当前请求与响应之间的地址匹配以及以前的请求和响应。 表格存储有关先前请求的更多具体信息。

公开(公告)号：US06684381B1

公开(公告)日：2004-01-27

申请号：US09675725

申请日：2000-09-29

申请人： Lionel Bening ,  Bryan Hornung ,  Robert Pflederer

发明人： Lionel Bening ,  Bryan Hornung ,  Robert Pflederer

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of providing hardware description language-embedded regular expression support for module iteration and interconnection. Regular expressions such as those used in the Perl programming language are used in a preprocessing process to generate instances and interconnections in a hardware description to automate the generation of repetitive code for a Hardware Description Language (HDL). This is accomplished by generating HDL code with embedded regular expressions, analyzing the code to identify the regular expressions and checking to see that the code complies with the HDL grammar rules. A data structure is generated for each module or submodule and these data structures are then elaborated to expand them into the instances and interconnections. A text generator traverses the elaborated data structures and generates HDL compliant text.

摘要翻译： 一种为模块迭代和互连提供硬件描述语言嵌入式正则表达式支持的方法。 用于Perl编程语言的正则表达式用于预处理过程，以在硬件描述中生成实例和互连，以自动生成硬件描述语言（HDL）的重复代码。 这是通过使用嵌入式正则表达式生成HDL代码来实现的，分析代码以识别正则表达式，并检查代码是否符合HDL语法规则。 为每个模块或子模块生成数据结构，然后详细阐述这些数据结构，将其扩展到实例和互连中。 文本生成器遍历详细的数据结构并生成符合HDL的文本。