公开(公告)号：US08270219B2

公开(公告)日：2012-09-18

申请号：US12826936

申请日：2010-06-30

Applicant: Byoung In Joo

Inventor： Byoung In Joo

IPC: G11C16/04

CPC classification number: G11C11/5642

Abstract: A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data.

Abstract translation: 通过接收双平面读取命令来操作非易失性存储器件，用于同时读取第一和第二平面，每个平面包括存储器单元，接收用于读取存储在存储器单元中的数据的MSB读取地址，检查是否执行了MSB编程操作 每个第一和第二平面，并且根据检查的结果对第一和第二平面执行读取操作并输出读取的数据。

公开(公告)号：US08228740B2

公开(公告)日：2012-07-24

申请号：US12814451

申请日：2010-06-12

Applicant: Byoung In Joo

Inventor： Byoung In Joo

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G06F11/1048 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

Abstract: A nonvolatile memory device is operated by, inter alia, performing a program operation on memory cells belonging to a page selected from among a plurality of pages, performing a verification operation on the programmed memory cells, loading a start loop value of a fail bit count set to the selected page, from among start loop values of fail bit counts set to the respective pages, and if a loop value of the program operation is greater than or equal to the start loop value, counting a number of fail bits included in data of the programmed memory cells detected in the verification operation.

Abstract translation: 非易失性存储器件通过尤其对属于从多个页面中选择的页面的存储器单元执行编程操作来操作，对所编程的存储器单元执行验证操作，加载故障位计数的启动循环值 设置到所选择的页面，从设置到各个页面的故障位计数的起始循环值中，并且如果程序操作的循环值大于或等于起始循环值，则对包含在数据中的故障位数进行计数 在验证操作中检测到​​的编程存储器单元。

公开(公告)号：US07668030B2

公开(公告)日：2010-02-23

申请号：US12117703

申请日：2008-05-08

Applicant: Byoung In Joo

Inventor： Byoung In Joo

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C7/12

Abstract: A method of operating a non-volatile memory device reduces a time for discharging a precharged voltage when a program operation or a read operation is performed, thereby decreasing a total operation time of the non-volatile memory device. The non-volatile memory device discharges a bit line and a word line using only a control signal without reading an algorithm block when a precharged voltage is discharged. The method of operating a non-volatile memory device includes detecting an operation command; generating algorithm blocks for generating an operation voltage, for precharging a bit line and a word line, and for performing a specific operation in accordance with the operation command; outputting a discharge enable control signal for the bit line and the word line; and reading an algorithm of turning off and discharging a voltage generating means for generating the operation voltage.

Abstract translation: 操作非易失性存储器件的方法在执行程序操作或读取操作时减少了放电预充电电压的时间，从而减少了非易失性存储器件的总操作时间。 当预充电电压放电时，非易失性存储器件仅使用控制信号放电位线和字线而不读取算法块。 操作非易失性存储装置的方法包括检测操作命令; 产生用于产生操作电压的算法块，用于对位线和字线进行预充电，并且用于根据操作命令执行特定操作; 输出位线和字线的放电使能控制信号; 以及读取关闭和放电用于产生操作电压的电压产生装置的算法。

公开(公告)号：US08873315B2

公开(公告)日：2014-10-28

申请号：US13615951

申请日：2012-09-14

Applicant: Byoung In Joo

Inventor： Byoung In Joo

IPC: G11C16/06

CPC classification number: G11C11/5642 ,  G11C16/06 ,  G11C16/3454

Abstract: The present disclosure relates to a semiconductor memory device and a method of operation the semiconductor memory device, which sets an encoding value by sequentially defining ranges used for recognizing distribution of memory cells based on a middle range and then performing a read operation in an order from the middle ranges to an outermost range, thereby capable of using infinite ranges for recognizing the distribution of the memory cells without addition of a circuit to an inside of the semiconductor memory device.

Abstract translation: 半导体存储器件和半导体存储器件的操作方法技术领域本公开涉及一种半导体存储器件和半导体存储器件的操作方法，该半导体存储器件通过依次定义用于识别基于中间范围的存储器单元的分配的范围来设置编码值，然后以从 中间范围到最外面的范围，从而能够使用无限范围来识别存储器单元的分布，而不向半导体存储器件的内部添加电路。