公开(公告)号：US20100133586A1

公开(公告)日：2010-06-03

申请号：US12463011

申请日：2009-05-08

申请人： Byoung-Gue MIN ,  Jong-Min Lee ,  Seong-II Kim ,  Kyung-Ho Lee ,  Hyung-Sup Yoon ,  Eun-Soo Nam

发明人： Byoung-Gue MIN ,  Jong-Min Lee ,  Seong-II Kim ,  Kyung-Ho Lee ,  Hyung-Sup Yoon ,  Eun-Soo Nam

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/42304 ,  H01L29/41708 ,  H01L29/66318 ,  H01L29/7371

摘要： Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and the emitter capping pattern being provided to a substrate; patterning a protection insulation layer and a first dummy pattern covering the emitter electrode, the base electrode, and the collector electrode, to expose the emitter electrode, the base electrode, and the collector electrode; forming a second dummy pattern to electrically separate the emitter electrode, the base electrode, and the collector electrode; forming, on the substrate provided with the second dummy pattern, an emitter electrode interconnection connected to the emitter electrode, a base electrode interconnection connected to the base electrode, and a collector electrode interconnection connected to the collector electrode; and removing the first and second dummy patterns.

摘要翻译： 提供了一种异质结双极晶体管及其形成方法。 该方法包括在发射极盖图案上形成发射电极，在基底图案上形成基极，在子集电极图案上形成集电极，将子集电极图案，基底图案，发射极图案和发射极封盖图案设置在 底物; 图案化保护绝缘层和覆盖发射电极，基极和集电极的第一虚拟图案，以暴露发射极，基极和集电极; 形成第二虚设图形以电分离发射电极，基极和集电极; 在设置有第二虚设图案的基板上形成连接到发射极的发射极电极互连，与基极连接的基极互连和与集电极连接的集电极互连; 以及去除第一和第二虚拟图案。

公开(公告)号：US5970328A

公开(公告)日：1999-10-19

申请号：US961407

申请日：1997-10-30

申请人： Byung-Sun Park ,  Jin-Hee Lee ,  Hyung-Sup Yoon ,  Chul-Sun Park ,  Kwang-Eui Pyun

发明人： Byung-Sun Park ,  Jin-Hee Lee ,  Hyung-Sup Yoon ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/335 ,  H01L29/423 ,  H01L21/338

CPC分类号： H01L29/66462 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/42316

摘要： A method for fabricating a T-shaped gate electrode of a high speed semiconductor device such as HEMTs which is applied to high speed logic circuit including low-noise receivers and power amplifiers having a frequency of X-band or more respectively, and MMICs having a frequency of millimeter wave band. Such devices require a short gate length and a large sectional area of the gate pattern. The conventional photolithography techniques are in need of the resolution for fabricating a fine line width. Therefore, electron-beam lithography is most widely used. But, it is difficult to enhance throughput in manufacturing semiconductor devices because a lot of exposure time is required in the methods using electron beams. In the present invention, a silicon oxide film or a silicon nitride film is deposited on a mono-layered resist pattern. A dummy pattern corresponding to a leg of the gate is formed using the silicon oxide film or the silicon nitride film. A leg of the gate electrode is formed at the portion of the dummy pattern. According to the present invention, a step for improving the resolution is not required, and a gate electrode having a very fine line width of a few hundreds .ANG. can be obtained by regulating the thickness of the silicon nitride film.

摘要翻译： 一种用于制造诸如HEMT的高速半导体器件的T形栅极的方法，其应用于包括具有X频带或更多频率的低噪声接收机和功率放大器的高速逻辑电路，以及具有 毫米波段的频率。 这样的器件需要栅极长度短和栅极图案的大截面积。 常规的光刻技术需要用于制造细线宽度的分辨率。 因此，电子束光刻被广泛使用。 但是，由于在使用电子束的方法中需要大量的曝光时间，所以难以提高制造半导体器件的吞吐量。 在本发明中，在单层抗蚀剂图案上沉积氧化硅膜或氮化硅膜。 使用氧化硅膜或氮化硅膜形成对应于栅极支脚的虚拟图案。 栅电极的一条腿形成在虚拟图案的部分。 根据本发明，不需要提高分辨率的步骤，并且可以通过调节氮化硅膜的厚度来获得具有几百安培的极细线宽的栅电极。

公开(公告)号：US5885847A

公开(公告)日：1999-03-23

申请号：US835957

申请日：1997-04-11

申请人： Hyung-Sup Yoon ,  Jin-Hee Lee ,  Byung-Sun Park ,  Chul-Sun Park ,  Kwang-Eui Pyun

发明人： Hyung-Sup Yoon ,  Jin-Hee Lee ,  Byung-Sun Park ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC分类号： H01L29/778 ,  H01L21/20 ,  H01L21/205 ,  H01L27/144 ,  H01L21/00 ,  H01L21/338

CPC分类号： H01L27/1443

摘要： The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate. The method comprises the steps of sequentially forming a plurality of first epitaxial layers for manufacturing the first compound semiconductor device on the semiconductor substrate; forming a first insulating film pattern for defining an active region of the first compound semiconductor device; etching the plurality of first epitaxial layers using the first insulating film pattern as a mask; forming a second insulating film on the resultant structure; forming a sidewall insulating spacer on the sidewall of the active region of the first compound semiconductor device by dry etching the second insulating film; sequentially forming a plurality of second epitaxial layers for manufacturing the second compound semiconductor device on the portion from which the plurality of first epitaxial layers is etched back; forming each electrode of the first and second compound semiconductor devices; and forming an interconnection electrode interconnecting each electrode of the first and second compound semiconductor devices.

摘要翻译： 本发明涉及通过在公共半导体衬底上形成具有多个不同外延层的第一和第二化合物半导体器件来制造化合物半导体器件的方法。 该方法包括以下步骤：在半导体衬底上依次形成用于制造第一化合物半导体器件的多个第一外延层; 形成用于限定所述第一化合物半导体器件的有源区的第一绝缘膜图案; 使用第一绝缘膜图案作为掩模蚀刻多个第一外延层; 在所得结构上形成第二绝缘膜; 通过干蚀刻所述第二绝缘膜，在所述第一化合物半导体器件的有源区的侧壁上形成侧壁绝缘间隔物; 在多个第一外延层被回蚀的部分上依次形成用于制造第二化合物半导体器件的多个第二外延层; 形成第一和第二化合物半导体器件的每个电极; 以及形成互连所述第一和第二化合物半导体器件的每个电极的互连电极。

公开(公告)号：US5702975A

公开(公告)日：1997-12-30

申请号：US719876

申请日：1996-09-25

申请人： Hyung-Sup Yoon ,  Jin-Hee Lee ,  Chul-Sun Park ,  Kwang-Eui Pyun

发明人： Hyung-Sup Yoon ,  Jin-Hee Lee ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC分类号： H01L29/40 ,  H01L21/285 ,  H01L21/335 ,  H01L21/76 ,  H01L21/302

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L21/7605

摘要： A method for isolating a semiconductor device is disclosed including the steps of sequentially growing a plurality of material layers on a semiconductor substrate, etching the material layers down to a predetermined depth of the substrate to thereby define an active region, forming a semi-insulating film on the exposed semiconductor substrate in order to planarize the step-difference of the active region and the isolation region, and then, forming an ohmic metal layer on a space where the semi-insulating film is regrown.

摘要翻译： 公开了一种用于隔离半导体器件的方法，包括以下步骤：在半导体衬底上顺序生长多个材料层，将材料层蚀刻到衬底的预定深度，从而限定有源区，形成半绝缘膜 在露出的半导体衬底上，以平坦化有源区和隔离区的阶梯差，然后在再次生长半绝缘膜的空间上形成欧姆金属层。