公开(公告)号：US5861327A

公开(公告)日：1999-01-19

申请号：US889939

申请日：1997-07-10

Applicant: Sung-Jae Maeng ,  Jae-Jin Lee ,  Kwang-Eui Pyun

Inventor： Sung-Jae Maeng ,  Jae-Jin Lee ,  Kwang-Eui Pyun

IPC: H01L21/336 ,  H01L21/027 ,  H01L21/285 ,  H01L21/338

CPC classification number: H01L29/66863 ,  H01L21/0274 ,  H01L21/28581 ,  H01L21/28587

Abstract: A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.

Abstract translation: 公开了一种半导体器件的制造方法。 在制造超高频和低噪声器件时采用了用于降低栅极电阻的T形栅极。 根据本发明，通过双重曝光技术形成栅极图案，形成薄金属膜，形成用于电镀的图案，并且通过电镀形成栅极，从而减小栅极长度和栅极电阻。 因此，生产成本降低，产量提高，噪音指标最小化。

公开(公告)号：US5702975A

公开(公告)日：1997-12-30

申请号：US719876

申请日：1996-09-25

Applicant: Hyung-Sup Yoon ,  Jin-Hee Lee ,  Chul-Sun Park ,  Kwang-Eui Pyun

Inventor： Hyung-Sup Yoon ,  Jin-Hee Lee ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC: H01L29/40 ,  H01L21/285 ,  H01L21/335 ,  H01L21/76 ,  H01L21/302

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L21/7605

Abstract: A method for isolating a semiconductor device is disclosed including the steps of sequentially growing a plurality of material layers on a semiconductor substrate, etching the material layers down to a predetermined depth of the substrate to thereby define an active region, forming a semi-insulating film on the exposed semiconductor substrate in order to planarize the step-difference of the active region and the isolation region, and then, forming an ohmic metal layer on a space where the semi-insulating film is regrown.

Abstract translation: 公开了一种用于隔离半导体器件的方法，包括以下步骤：在半导体衬底上顺序生长多个材料层，将材料层蚀刻到衬底的预定深度，从而限定有源区，形成半绝缘膜 在露出的半导体衬底上，以平坦化有源区和隔离区的阶梯差，然后在再次生长半绝缘膜的空间上形成欧姆金属层。

公开(公告)号：US5696007A

公开(公告)日：1997-12-09

申请号：US729840

申请日：1996-10-15

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/70 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/072

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.

Abstract translation: 本发明涉及一种能够使元件小型化的超自对准异质结双极晶体管的制造方法，通过采用选择性集电体外延生长和多选择性基极电极简化其工艺步骤，而不使用用于隔离元件之间的沟槽， 从而提高其性能，其包括以下步骤：在衬底的顶部上顺次形成第一氧化膜，导电薄膜和第二氧化膜; 图案化第二氧化膜和导电薄膜以形成预备间隔物; 去除第一氧化膜的暴露部分，并选择性地生长集电体层; 氧化所述集电体层以形成热氧化膜，并除去所述预备间隔物; 在所述第二氧化膜上分别沉积多晶硅并形成硅氧化膜和多晶硅间隔物和所述预备间隔物的去除部分; 暴露基底薄膜，间隔物和集电极层以形成SiGe / Si层; 在SiGe / Si层上形成基极; 暴露第一氧化膜的一部分并形成第三氧化膜; 暴露SiGe / Si层的表面并在蚀刻部分的侧面上形成氧化间隔物，然后自发对准发射极和发射极; 并执行金属布线处理。

公开(公告)号：US5496779A

公开(公告)日：1996-03-05

申请号：US358886

申请日：1994-12-19

Applicant: Kyung-Ho Lee ,  Youn-Kyu Bae ,  Kwang-Eui Pyun ,  Kyung-Soo Kim

Inventor： Kyung-Ho Lee ,  Youn-Kyu Bae ,  Kwang-Eui Pyun ,  Kyung-Soo Kim

IPC: H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L21/265

CPC classification number: H01L29/66878 ,  H01L21/28587

Abstract: Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern of a photo-resist film to form a self-aligned high concentration ion implantation region, forming a third insulation layer for preventing As of evaporation, carrying out a rapid thermal annealing for activation, removing the third insulation layer; and forming an ohmic electrode using a lift-off process.

Abstract translation: 公开了一种制造金属半导体场效应晶体管的方法，包括以下步骤：使用离子注入形成沟道，顺序地形成第一预定温度的第一绝缘体层和在表面上的第二预定温度的第二绝缘层 使用光致抗蚀剂图案的栅极图案蚀刻第一绝缘层和第二绝缘层以暴露沟道区域作为掩模，在第一和第二绝缘层的表面上形成耐火金属添加暴露的沟道区， 蚀刻耐火金属，从而将其分成两部分，其中一部分形成在沟道区上，另一部分形成在第二绝缘层上，选择性地蚀刻第一绝缘层和第二绝缘层以在第一绝缘层上剥离难熔金属， 第二绝缘层，从而在沟道区上形成T形栅极，使用ga将Si离子注入衬底 和形成自对准高浓度离子注入区的通道图案，形成用于防止As蒸发的第三绝缘层，进行激活的快速热退火，去除第三绝缘层; 并使用剥离工艺形成欧姆电极。

公开(公告)号：US6100753A

公开(公告)日：2000-08-08

申请号：US137886

申请日：1998-08-21

Applicant: Chang Seok Lee ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Chang Seok Lee ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H01L29/70 ,  G05F3/24 ,  G05F1/10

CPC classification number: G05F3/247 ,  G05F3/245

Abstract: The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature. In the present invention, the above problem is solved by configuring a level shifter circuit between the drain node and the gate node of the reference voltage generation transistor. Further, by using a constant current source utilizing a depletion transistor and series feedback resistors as a reference current, this circuit becomes stable against the variations of the device parameters as well as the variations of the temperature and supply voltage.

Abstract translation: 本发明涉及一种偏置稳定电路，特别涉及一种偏置稳定电路，用于使由场效应晶体管制造高频集成电路期间发生的器件参数变化引起的放大晶体管的电流变化最小化，并由 电源电压和温度变化。 在本发明中，通过在基准电压产生晶体管的漏极节点和栅极节点之间配置电平移位电路来解决上述问题。 此外，通过使用利用耗尽晶体管和串联反馈电阻器的恒流源作为参考电流，该电路针对器件参数的变化以及温度和电源电压的变化而变得稳定。

公开(公告)号：US6064265A

公开(公告)日：2000-05-16

申请号：US146529

申请日：1998-09-03

Applicant: Kwang Jun Yun ,  Min Kun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Kwang Jun Yun ,  Min Kun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H03F3/193 ,  H03G1/00 ,  H03G3/30 ,  H03G3/10

CPC classification number: H03F3/193 ,  H03G1/007 ,  H03G3/3042 ,  H03F2200/294 ,  H03F2200/318

Abstract: The present invention relates to a gain control circuit for a low-noise amplifier. A gain control circuit of a 2-stage low-noise amplifier comprising an input stage noise matching circuit, an intermediate impedance matching circuit, a gain control circuit, and an output stage impedance matching circuit, said gain control circuit including: a feedback circuit connected to a transistor of second stage of the 2-stage low-noise amplifier, said feedback circuit detecting the amplified signal through the first stage and the second stage, and feeding the signal back through a switch circuit; and an attenuation circuit for compensating the harmonics of the input signal.

Abstract translation: 本发明涉及一种用于低噪声放大器的增益控制电路。 一种包括输入级噪声匹配电路，中间阻抗匹配电路，增益控制电路和输出级阻抗匹配电路的2级低噪声放大器的增益控制电路，所述增益控制电路包括：反馈电路， 到2级低噪声放大器的第二级的晶体管，所述反馈电路通过第一级和第二级检测放大的信号，并通过开关电路将信号反馈; 以及用于补偿输入信号的谐波的衰减电路。

公开(公告)号：US5939954A

公开(公告)日：1999-08-17

申请号：US955378

申请日：1997-10-21

Applicant: Min Gun Kim ,  Choong Hwan Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Min Gun Kim ,  Choong Hwan Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H01L23/28 ,  H03H7/38 ,  H01L23/64 ,  H05K7/02

CPC classification number: H03H7/38 ,  H01L2224/45144 ,  H01L2224/48091

Abstract: The present invention relates to an equivalent circuit of a package ground terminal paddle which is used to mount a microwave integrated circuit, and more particularly, to an approximate equivalent circuit of the package ground terminal paddle by which the expressions of parasitic components can be easily expanded according to the number of gold wires that are down-bonded to the paddle, by introducing an equivalent circuit structure which takes the impedance component output from each terminal as one common impedance component and grounds the common impedance.

Abstract translation: 本发明涉及一种用于安装微波集成电路的封装接地端子板的等效电路，更具体地说涉及封装接地端子板的近似等效电路，通过该电路可以容易地扩展寄生元件的表达 根据下焊接到焊盘的金线的数量，通过引入等效电路结构，其将来自每个端子的阻抗分量输出作为一个公共阻抗分量并将公共阻抗接地。

公开(公告)号：US06190984B1

公开(公告)日：2001-02-20

申请号：US09229831

申请日：1999-01-13

Applicant: Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Deok-Ho Cho ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L218222

CPC classification number: H01L29/66242

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract translation: 本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。 根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。 基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。 此外，不需要基底的选择性外延生长。 因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

公开(公告)号：US6057736A

公开(公告)日：2000-05-02

申请号：US135576

申请日：1998-08-18

Applicant: Min Gun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Min Gun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H03G1/00 ,  H03F1/34 ,  H03G3/30

CPC classification number: H03F1/342 ,  H03G1/007 ,  H03F2200/151

Abstract: The present invention relates to a gain controlled amplifier, and more particularly, to a gain controlled amplifier using active feedback and variable resistance. It is an object of the present invention to provide a gain controlled amplifier minimizing the gain and the degradation of power characteristics generated when adjusting gain in a variable gain amplifier which receives signals having different power levels, amplifies them in accordance with each power level and outputs output signals in a constant power level. In order to achieve the above object, a gain controlled amplifier in accordance with the present invention comprises an amplifier and an active feedback means for negative feedbacking the output of the amplifier to the input of the amplifier, and further has a feedback amount controller inputting the controlled feedback signal to the amplifier by controlling the feedback amount of said active feedback means.

Abstract translation: 增益控制放大器本发明涉及一种增益控制放大器，更具体地说，涉及一种使用有源反馈和可变电阻的增益控制放大器。 本发明的一个目的是提供一种增益控制放大器，其最大程度地减小在接收具有不同功率电平的信号的可变增益放大器中调节增益时产生的功率特性的增益和劣化，根据每个功率电平放大它们 输出信号处于恒定功率电平。 为了实现上述目的，根据本发明的增益控制放大器包括放大器和用于将放大器的输出负反馈到放大器的输入的有源反馈装置，并且还具有反馈量控制器，其输入 通过控制所述主动反馈装置的反馈量来控制反馈信号到放大器。

公开(公告)号：US5972232A

公开(公告)日：1999-10-26

申请号：US984148

申请日：1997-12-03

Applicant: Sang Hwan Lee ,  Nam Hwang ,  Min Kyu Song ,  Hee Tae Lee ,  Kwang Eui Pyun

Inventor： Sang Hwan Lee ,  Nam Hwang ,  Min Kyu Song ,  Hee Tae Lee ,  Kwang Eui Pyun

IPC: G02B6/35 ,  G02B6/12 ,  G02B6/122 ,  G02B6/42 ,  H01L21/00

CPC classification number: G02B6/122 ,  G02B6/4214 ,  G02B2006/12104 ,  G02B6/4224 ,  G02B6/4232 ,  G02B6/4249

Abstract: Disclosed is a micromirror for a hybrid optoelectronic integrated circuit, a method for manufacturing the same, a micromirror-photodetector assembly and an assembly of hybrid optoelectronic integrated circuit for receiving light. The micromirror the present invention comprises a silicon substrate and at least one V-shaped groove formed in the silicon substrate and the V-shaped groove has an inclined surface reflecting light emitted from an optical waveguide to a photodetector. The alignment of the photodetector and the optical fibers is achieved without an additional attachment equipment, by inserting the optical fibers into the V-groove.

Abstract translation: 公开了一种用于混合光电集成电路的微镜，其制造方法，微镜光电检测器组件和用于接收光的混合光电集成电路的组件。 本发明的微反射镜包括硅衬底和形成在硅衬底中的至少一个V形槽，并且V形槽具有将从光波导发射的光反射到光电检测器的倾斜表面。 通过将光纤插入到V形槽中，可以实现光电检测器和光纤的对准而无需额外的附接设备。