公开(公告)号：US20070031997A1

公开(公告)日：2007-02-08

申请号：US11499370

申请日：2006-08-04

申请人： Byoung-hun Lee ,  Ho-min Kang ,  Hoon-kee Min ,  Jeong-ho Hwang ,  Sung-min Kim

发明人： Byoung-hun Lee ,  Ho-min Kang ,  Hoon-kee Min ,  Jeong-ho Hwang ,  Sung-min Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/67363

摘要： Provided is a jig which can be used in a process of adhering a adhering object to a to-be adhered object in a vacuum atmosphere, and vacuum equipment for use in the adhering process. The jig includes a first frame and a second frame which together define a chamber for receiving the first and second objects. The first frame includes a seating portion having a plurality of seating pockets, and an actuator disposed below each of the seating pockets, the actuator being movable with respect to the seating pockets. A first elastic member is disposed in the jig below the actuator. The first elastic member being positioned such that it can contact and move the actuator in response to a change of pressure in the jig chamber. The second frame includes a second elastic member which is positioned adjacent to each of the seating pockets. The second elastic member being movable to the change of pressure in the jig chamber.

摘要翻译： 提供了一种夹具，其可用于在真空气氛中将粘附物粘附到待粘合物体的过程中，以及用于粘合过程的真空设备。 夹具包括第一框架和第二框架，第一框架和第二框架共同限定用于接收第一和第二物体的室。 第一框架包括具有多个座舱的座位部分和设置在每个座舱下方的致动器，所述致动器可相对于所述座舱口移动。 第一弹性构件设置在致动器下方的夹具中。 第一弹性构件被定位成使得其可以响应于夹具室中的压力变化而接触和移动致动器。 第二框架包括第二弹性构件，该第二弹性构件邻近每个座舱口定位。 第二弹性构件可移动到夹具室中的压力变化。

公开(公告)号：US08908052B2

公开(公告)日：2014-12-09

申请号：US12949169

申请日：2010-11-18

申请人： Sung-min Kim ,  Jin-gi Lee

发明人： Sung-min Kim ,  Jin-gi Lee

IPC分类号： H04N5/232

CPC分类号： H04N5/23248 ,  H04N5/23258 ,  H04N5/23261

摘要： Provided is a method, apparatus, and computer readable medium for correcting shakiness, in which the method includes generating using a hall sensor a hall sensor signal corresponding to displacement caused by a shock; determining whether the hall sensor signal exceeds a first threshold value; generating a shakiness correction control signal according to a result of the determination; and performing shakiness correction according to the shakiness correction control signal.

摘要翻译： 提供了一种用于校正抖动的方法，装置和计算机可读介质，其中该方法包括使用霍尔传感器产生对应于由冲击引起的位移的霍尔传感器信号; 确定所述霍尔传感器信号是否超过第一阈值; 根据确定的结果产生抖动校正控制信号; 并根据抖动校正控制信号进行抖动校正。

公开(公告)号：US08046054B2

公开(公告)日：2011-10-25

申请号：US11530653

申请日：2006-09-11

申请人： Young Soo Kim ,  Byung-Ju Yi ,  Jong-Il Park ,  Sung-min Kim ,  Se-Min Oh

发明人： Young Soo Kim ,  Byung-Ju Yi ,  Jong-Il Park ,  Sung-min Kim ,  Se-Min Oh

IPC分类号： A61B5/05

CPC分类号： A61B6/4014 ,  A61B6/4441 ,  A61B34/10 ,  A61B34/30 ,  A61B2090/376

摘要： Disclosed is a computer-integrated surgery aid system for minimally invasive surgery and a method for controlling the same. The system includes a surgery planning system for creating three-dimensional information from two-dimensional images obtained by means of biplanar fluoroscopy so that spinal surgery can be planned according to the image information and a scalar-type 6 degree-of-freedom surgery aid robot adapted to be either driven automatically or operated manually.

摘要翻译： 公开了一种用于微创手术的计算机一体化手术辅助系统及其控制方法。 该系统包括用于通过双平面荧光透视获得的二维图像创建三维信息的手术计划系统，使得可以根据图像信息和标量型6自由度手术辅助机器人计划脊柱手术 适于自动驱动或手动操作。

公开(公告)号：US08008141B2

公开(公告)日：2011-08-30

申请号：US12503594

申请日：2009-07-15

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L21/8232

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US20090239346A1

公开(公告)日：2009-09-24

申请号：US12477348

申请日：2009-06-03

申请人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。 具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。 第一突起和第二突起的上表面和侧表面包括通道区域。 通道离子注入层设置在中央沟槽的底部和鳍片的下部。 在鳍片上设置栅极氧化层。 栅电极设置在栅氧化层上。 源极区域和漏极区域设置在栅电极侧的有源区域中。 还提供了一种形成这种装置的方法。

公开(公告)号：US20090168493A1

公开(公告)日：2009-07-02

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00 ,  H01L21/00 ,  H01L47/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US07442987B2

公开(公告)日：2008-10-28

申请号：US12014276

申请日：2008-01-15

申请人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

摘要翻译： 半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。 该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层， 第一和第二电荷存储层。 栅电极远离基板延伸超过第一和第二电荷存储层。 该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。 还讨论了相关的制造方法。

公开(公告)号：US07402483B2

公开(公告)日：2008-07-22

申请号：US11190695

申请日：2005-07-26

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66772

摘要： A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenches run across the stacked structure parallel to each other and separate a first stacked portion including channel patterns and interchannel patterns from second stacked portions including channel and interchannel layers remaining on both sides of the first stacked portion. First source and drain regions are grown using selective epitaxial growth. The first source and drain regions fill the trenches and connect to second source and drain regions defined by the second stacked portions. Marginal sections of the interchannel patterns of the first stacked portion are selectively exposed. Through tunnels are formed by selectively removing the interchannel patterns of the first stacked portion beginning with the exposed marginal sections. The through tunnels are surrounded by the first source and drain regions and the channel patterns. A gate is formed along with a gate dielectric layer, the gate filling the through tunnels and extending onto the first stacked portion.

摘要翻译： 可以通过在包括沟道层和介于沟道层之间的沟道间层的衬底上形成层叠结构来形成多桥沟MOSFET（MBCFET）。 通过选择性地蚀刻堆叠结构形成沟槽。 沟槽横跨层叠结构彼此平行地延伸，并且将包括通道图案和沟道间图案的第一堆叠部分与第二堆叠部分分开，包括残留在第一堆叠部分两侧的通道和通道间层。 使用选择性外延生长生长第一源区和漏区。 第一源极和漏极区域填充沟槽并连接到由第二堆叠部分限定的第二源极和漏极区域。 选择性地暴露第一堆叠部分的通道间图案的边缘部分。 通过从暴露的边缘部分开始选择性地去除第一堆叠部分的通道间图案，形成通道。 穿通隧道被第一源极和漏极区域以及沟道图案包围。 栅极与栅极电介质层一起形成，栅极填充通孔并延伸到第一堆叠部分上。

公开(公告)号：US20070200178A1

公开(公告)日：2007-08-30

申请号：US11783518

申请日：2007-04-10

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L27/12

CPC分类号： H01L29/66553 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/7831

摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

公开(公告)号：US07253060B2

公开(公告)日：2007-08-07

申请号：US11074711

申请日：2005-03-09

申请人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

发明人： Eun-jung Yun ,  Sung-min Kim ,  Sung-young Lee

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78654

摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.

摘要翻译： 栅极全能（GAA）晶体管器件具有一对支柱，其包括源极/漏极区域，桥接源极/漏极区域的沟道区域以及围绕沟道区域的栅极电极和栅极氧化物。 支柱通过提供单晶硅衬底形成，蚀刻衬底以形成一对隔开的沟槽，使得单晶硅的壁站立在沟槽之间，用绝缘材料填充沟槽，将杂质注入 单晶硅的壁，并且在壁中形成开口，使得壁的一部分保持为支柱。 牺牲层形成在开口的底部。 然后，通道区域形成在支柱之间的牺牲层的顶部。 随后去除牺牲层，并且在沟道区周围形成栅极氧化物和栅电极。 使用一个或多个侧壁间隔物来建立沟道区域的有效宽度和/或最小化源极/漏极区域和栅电极之间的寄生电容。