公开(公告)号：US07602010B2

公开(公告)日：2009-10-13

申请号：US11407133

申请日：2006-04-19

申请人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

发明人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851

摘要： In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.

摘要翻译： 在允许多位和/或多电平操作的非易失性存储器件及其操作和制造方法中，非易失性存储器件在一个实施例中包括：半导体衬底，掺杂有第一 导电型，其具有由形成在基板中的至少两个分开的沟槽限定的一个或多个散热片，散热片沿第一方向沿着基板延伸; 成对的栅电极在散热片的侧壁处形成为间隔物，其中栅电极与包括散热片的半导体基板绝缘，并平行于翅片延伸; 栅电极和鳍之间的存储节点，并与栅电极和半导体衬底绝缘; 源极区域和漏极区域，其掺杂有第二导电类型的杂质，并且分别形成在鳍片的至少在表面部分并且延伸穿过翅片的第一方向; 以及对应于各个栅电极的沟道区，至少在源极和漏极区之间的翅片的侧壁的表面区域处形成。

公开(公告)号：US20060249779A1

公开(公告)日：2006-11-09

申请号：US11407133

申请日：2006-04-19

申请人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

发明人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851

摘要： In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.

公开(公告)号：US20070190725A1

公开(公告)日：2007-08-16

申请号：US11740525

申请日：2007-04-26

申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

公开(公告)号：US20060131613A1

公开(公告)日：2006-06-22

申请号：US11240544

申请日：2005-09-30

申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

IPC分类号： H01L27/10

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

公开(公告)号：US07227220B2

公开(公告)日：2007-06-05

申请号：US11240544

申请日：2005-09-30

申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

公开(公告)号：US07675105B2

公开(公告)日：2010-03-09

申请号：US11376518

申请日：2006-03-15

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US07939408B2

公开(公告)日：2011-05-10

申请号：US12970475

申请日：2010-12-16

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US20110086483A1

公开(公告)日：2011-04-14

申请号：US12970475

申请日：2010-12-16

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US20060214219A1

公开(公告)日：2006-09-28

申请号：US11376518

申请日：2006-03-15

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US07875921B2

公开(公告)日：2011-01-25

申请号：US12692197

申请日：2010-01-22

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.