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公开(公告)号：US11862723B2
公开(公告)日：2024-01-02
申请号：US17389898
申请日：2021-07-30
发明人： Qu Luo
CPC分类号： H01L29/7827 , H01L29/66666 , H10B12/05 , H10B12/315
摘要： A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.
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公开(公告)号：US11980024B2
公开(公告)日：2024-05-07
申请号：US17595618
申请日：2021-06-09
发明人： Qu Luo
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/053 , H10B12/488
摘要： The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor base, bit lines and word lines, wherein a plurality of active regions is provided in the semiconductor base; the bit lines are disposed in the semiconductor base, extend in a first direction and are connected to the active regions; and the word lines are disposed on the semiconductor base above the bit lines, extend in a second direction, and intersect with the active regions.
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公开(公告)号：US11871555B2
公开(公告)日：2024-01-09
申请号：US17386485
申请日：2021-07-27
发明人： Qu Luo , WenHao Hsieh
IPC分类号： H10B12/00
CPC分类号： H10B12/053 , H10B12/34
摘要： A semiconductor structure and method for forming the semiconductor structure are provided. The method includes: providing a semiconductor substrate, which has a plurality of independent active areas that are isolated from each other by shallow trench isolation areas; forming trenches by etching the active areas and the shallow trench isolation areas, the trenches include first trenches and second trenches, the first trenches are located in the active areas, the second trenches are located in the shallow trench isolation areas, and the first trenches have a width greater than a width of the second trenches; forming word lines in the trenches, the word lines include first word lines and second word lines, each first word line is located in the respective first trench, each second word line is located in the respective second trench, and the first word lines have a width greater than a width of the second word lines.
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公开(公告)号：US20210358920A1
公开(公告)日：2021-11-18
申请号：US17386485
申请日：2021-07-27
发明人： Qu Luo , WenHao Hsieh
IPC分类号： H01L27/108
摘要： A semiconductor structure and method for forming the semiconductor structure are provided. The method includes: providing a semiconductor substrate, which has a plurality of independent active areas that are isolated from each other by shallow trench isolation areas; forming trenches by etching the active areas and the shallow trench isolation areas, the trenches include first trenches and second trenches, the first trenches are located in the active areas, the second trenches are located in the shallow trench isolation areas, and the first trenches have a width greater than a width of the second trenches; forming word lines in the trenches, the word lines include first word lines and second word lines, each first word line is located in the respective first trench, each second word line is located in the respective second trench, and the first word lines have a width greater than a width of the second word lines.
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公开(公告)号：US12089393B2
公开(公告)日：2024-09-10
申请号：US17385043
申请日：2021-07-26
发明人： Qu Luo , WenHao Hsieh
IPC分类号： H01L27/108 , H01L21/8234 , H01L29/66 , H01L29/78 , H10B12/00
CPC分类号： H10B12/053 , H01L21/823437 , H01L29/66734 , H01L29/7813 , H10B12/34
摘要： A memory and a method for forming the same are provided. In the method, a word line trench is formed in active regions and an isolation layer. The formed word line trench includes a first partial word line trench located in the active regions and a second partial word line trench located in the isolation layer. The width and depth of the second partial word line trench are greater than the width and depth of the first partial word line trench respectively. Therefore, when a word line structure is formed in the word line trench, the formed word line structure also includes a first partial word line structure located in the first partial word line trench and a second partial word line structure located in the second partial word line trench.
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公开(公告)号：US20220077289A1
公开(公告)日：2022-03-10
申请号：US17455691
申请日：2021-11-19
发明人： Qu Luo , Cheng Yeh Hsu
IPC分类号： H01L29/40 , H01L29/423
摘要： Disclosed are a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a first wordline trench structure; forming a first sacrificial layer at the bottom of the first wordline trench structure; filling the first wordline trench structure located in active regions by epitaxial growth; forming a first insulation layer covering the top of the semiconductor substrate and the first wordline trench structure; forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a projection of the second wordline trench structure in a vertical direction completely overlapping with a projection of the first sacrificial layer in the vertical direction; removing the first sacrificial layer; and filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel.
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