公开(公告)号：US20220293722A1

公开(公告)日：2022-09-15

申请号：US17452788

申请日：2021-10-29

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Daejoong Won ,  Soonbyung Park ,  Er-Xuan Ping

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423

摘要： A semiconductor structure and a forming method thereof are disclosed in the embodiments of the present disclosure. The semiconductor structure includes: a base, wherein a gate dielectric layer defining a groove is provided in the base, a source region and a drain region are located on two opposite sides at a top of the groove, and the groove has an extension direction parallel to a surface of the base; a first gate, including a first work function layer and a first conductive layer, wherein the first work function layer covers a bottom surface and partial sidewall of the groove, and the first conductive layer covers a surface of the first work function layer; and a second gate, including a second work function layer and a second conductive layer, wherein the second gate is laminated on the first gate and has a top surface lower than the surface of the base.

公开(公告)号：US20240098975A1

公开(公告)日：2024-03-21

申请号：US18511808

申请日：2023-11-16

申请人： Changxin Memory Technologies, Inc.

发明人： Takao Adachi ,  Xiaoguang Wang ,  Deyuan Xiao ,  Soonbyung Park

IPC分类号： H10B12/00

CPC分类号： H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

摘要： A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.

公开(公告)号：US12094945B2

公开(公告)日：2024-09-17

申请号：US17452788

申请日：2021-10-29

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Daejoong Won ,  Soonbyung Park ,  Er-Xuan Ping

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/66621 ,  H01L29/7825

摘要： A semiconductor structure and a forming method thereof are disclosed in the embodiments of the present disclosure. The semiconductor structure includes: a base, wherein a gate dielectric layer defining a groove is provided in the base, a source region and a drain region are located on two opposite sides at a top of the groove, and the groove has an extension direction parallel to a surface of the base; a first gate, including a first work function layer and a first conductive layer, wherein the first work function layer covers a bottom surface and partial sidewall of the groove, and the first conductive layer covers a surface of the first work function layer; and a second gate, including a second work function layer and a second conductive layer, wherein the second gate is laminated on the first gate and has a top surface lower than the surface of the base.

公开(公告)号：US12048145B2

公开(公告)日：2024-07-23

申请号：US17602937

申请日：2021-07-08

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Daejoong Won ,  Soonbyung Park ,  Er-Xuan Ping

IPC分类号： H10B12/00

CPC分类号： H10B12/488 ,  H10B12/09

摘要： Embodiments of the present disclosure provide a method of manufacturing a semiconductor structure. The semiconductor structure includes a peripheral area and an array area, and the method of manufacturing a semiconductor structure includes: providing a substrate; where the substrate in the peripheral area includes an active layer; a first isolation layer is further provided on the active layer; forming a buried word line in the substrate in the array area; where a second isolation layer is further provided on the buried word line; the buried word line includes a first conductive layer and a second conductive layer; patterning the first isolation layer and the second isolation layer by dry etching to form first through holes and a second through hole; where the first through holes expose a top surface of the active layer, and the second through hole exposes the second conductive layer.