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公开(公告)号：US07657682B2
公开(公告)日：2010-02-02
申请号：US11855706
申请日：2007-09-14
IPC分类号： G06F12/00
CPC分类号： G06F13/362
摘要： A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.
摘要翻译： 提供了一种操作耦合到总线主机和总线从站的总线互连的方法。 该方法包括：接收来自总线主机的请求，以执行与多个总线从站的总线从站相关联的事务ID的总线事务，总线事务是第一类总线事务。 该方法还包括如果分配给总线主控器的资源分配参数达到第一阈值，则执行该事务。 所述方法还包括：如果所述资源分配参数不满足所述第一阈值，则仅当所述事务满足至少一个条件的集合的条件时执行所述数据事务，其中，所述至少一个条件的集合的条件包括： 事务的事务ID不是总线主控器请求的第一种类型的任何未完成总线事务的事务ID。
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2.发明授权Method and system for controlling transmission and execution of commands in an integrated circuit device 有权用于控制集成电路装置中的命令的传输和执行的方法和系统公开(公告)号：US08156273B2
公开(公告)日：2012-04-10
申请号：US11747087
申请日：2007-05-10
IPC分类号： G06F13/00 , G06F7/38 , G06F13/368 , G06F12/00 , G06F13/26
CPC分类号： G06F13/362
摘要： A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).
摘要翻译： 用于控制集成电路（IC）装置中的命令的传输和执行的方法和系统以其优先级顺序提供命令和确认的传送。 基于预先分配的主设备和从设备的优先级来定义命令和确认的优先级。 在一个应用中，本发明用于提高采用高级可扩展接口（AXI）的IC设备的性能。
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公开(公告)号：US20090077289A1
公开(公告)日：2009-03-19
申请号：US11855706
申请日：2007-09-14
IPC分类号： G06F13/00
CPC分类号： G06F13/362
摘要： A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.
摘要翻译： 提供了一种操作耦合到总线主机和总线从站的总线互连的方法。 该方法包括：接收来自总线主机的请求，以执行与多个总线从站的总线从站相关联的事务ID的总线事务，总线事务是第一类总线事务。 该方法还包括如果分配给总线主控器的资源分配参数达到第一阈值，则执行该事务。 所述方法还包括：如果所述资源分配参数不满足所述第一阈值，则仅当所述事务满足至少一个条件的集合的条件时执行所述数据事务，其中，所述至少一个条件的集合的条件包括： 事务的事务ID不是总线主控器请求的第一种类型的任何未完成总线事务的事务ID。
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4.发明申请METHOD AND SYSTEM FOR CONTROLLING TRANSMISSION and EXECUTION OF COMMANDS IN AN INTEGRATED CIRCUIT DEVICE 有权用于控制传输的方法和系统以及集成电路设备中的命令的执行公开(公告)号：US20080282007A1
公开(公告)日：2008-11-13
申请号：US11747087
申请日：2007-05-10
IPC分类号： G06F13/00
CPC分类号： G06F13/362
摘要： A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).
摘要翻译： 用于控制集成电路（IC）装置中的命令的传输和执行的方法和系统以其优先级顺序提供命令和确认的传送。 基于预先分配的主设备和从设备的优先级来定义命令和确认的优先级。 在一个应用中，本发明用于提高采用高级可扩展接口（AXI）的IC设备的性能。
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公开(公告)号：US07747889B2
公开(公告)日：2010-06-29
申请号：US11461048
申请日：2006-07-31
CPC分类号： H04L7/00 , H04L7/0008
摘要： A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
摘要翻译： 数据处理系统可以包括具有输出的发起者设备，其输出单独对应于沿着信令路径的第一延迟的时钟输入引用。 示例性数据处理系统还可以包括具有输入的目标设备，其输入单独对应于沿着信令路径的第二延迟的时钟输入和在信令路径内的起始设备和目标设备之间互连的系统总线 。 示例性数据处理系统还可以包括耦合到信令路径内的系统总线的动态定时桥，其中响应于表示至少一个系统特性的控制信号，动态定时桥执行从由（i ）在信令路径内插入循环延迟，并且（ii）不在信令路径内插入循环等待时间。
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公开(公告)号：US20090304134A1
公开(公告)日：2009-12-10
申请号：US12134913
申请日：2008-06-06
摘要： A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.
摘要翻译： 在第一同步器的数据输入处接收第一输入信号，第一数据输入与时钟同步。 在第二同步器的数据输入处接收第二输入信号，第二信号被同步到时钟。 防止在第一同步器的时钟输入处接收到转换，并且响应于在第一同步器的输出处具有与第一输出信号相同的逻辑值的第一输入信号，在第二同步器的时钟输入处接收到转换 同步器和第二输入信号在第二同步器的输出处具有与第二输出信号相同的逻辑值。
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公开(公告)号：US08363766B2
公开(公告)日：2013-01-29
申请号：US12134913
申请日：2008-06-06
IPC分类号： H04L7/00
摘要： A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.
摘要翻译： 在第一同步器的数据输入处接收第一输入信号，第一数据输入与时钟同步。 在第二同步器的数据输入处接收第二输入信号，第二信号被同步到时钟。 防止在第一同步器的时钟输入处接收到转换，并且响应于在第一同步器的输出处具有与第一输出信号相同的逻辑值的第一输入信号，在第二同步器的时钟输入处接收到转换 同步器和第二输入信号在第二同步器的输出处具有与第二输出信号相同的逻辑值。
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公开(公告)号：US20080028253A1
公开(公告)日：2008-01-31
申请号：US11461048
申请日：2006-07-31
IPC分类号： G06F1/04
CPC分类号： H04L7/00 , H04L7/0008
摘要： A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
摘要翻译： 数据处理系统可以包括具有输出的发起者设备，其输出单独对应于沿着信令路径的第一延迟的时钟输入引用。 示例性数据处理系统还可以包括具有输入的目标设备，其输入单独对应于沿着信令路径的第二延迟的时钟输入和在信令路径内的起始设备和目标设备之间互连的系统总线 。 示例性数据处理系统还可以包括耦合到信令路径内的系统总线的动态定时桥，其中响应于表示至少一个系统特性的控制信号，动态定时桥执行从由（i ）在信令路径内插入循环延迟，并且（ii）不在信令路径内插入循环等待时间。
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