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公开(公告)号：US20090304134A1
公开(公告)日：2009-12-10
申请号：US12134913
申请日：2008-06-06
摘要： A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.
摘要翻译： 在第一同步器的数据输入处接收第一输入信号，第一数据输入与时钟同步。 在第二同步器的数据输入处接收第二输入信号，第二信号被同步到时钟。 防止在第一同步器的时钟输入处接收到转换，并且响应于在第一同步器的输出处具有与第一输出信号相同的逻辑值的第一输入信号，在第二同步器的时钟输入处接收到转换 同步器和第二输入信号在第二同步器的输出处具有与第二输出信号相同的逻辑值。
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公开(公告)号：US08363766B2
公开(公告)日：2013-01-29
申请号：US12134913
申请日：2008-06-06
IPC分类号： H04L7/00
摘要： A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.
摘要翻译： 在第一同步器的数据输入处接收第一输入信号，第一数据输入与时钟同步。 在第二同步器的数据输入处接收第二输入信号，第二信号被同步到时钟。 防止在第一同步器的时钟输入处接收到转换，并且响应于在第一同步器的输出处具有与第一输出信号相同的逻辑值的第一输入信号，在第二同步器的时钟输入处接收到转换 同步器和第二输入信号在第二同步器的输出处具有与第二输出信号相同的逻辑值。
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公开(公告)号：US20080028253A1
公开(公告)日：2008-01-31
申请号：US11461048
申请日：2006-07-31
IPC分类号： G06F1/04
CPC分类号： H04L7/00 , H04L7/0008
摘要： A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
摘要翻译： 数据处理系统可以包括具有输出的发起者设备，其输出单独对应于沿着信令路径的第一延迟的时钟输入引用。 示例性数据处理系统还可以包括具有输入的目标设备，其输入单独对应于沿着信令路径的第二延迟的时钟输入和在信令路径内的起始设备和目标设备之间互连的系统总线 。 示例性数据处理系统还可以包括耦合到信令路径内的系统总线的动态定时桥，其中响应于表示至少一个系统特性的控制信号，动态定时桥执行从由（i ）在信令路径内插入循环延迟，并且（ii）不在信令路径内插入循环等待时间。
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公开(公告)号：US07747889B2
公开(公告)日：2010-06-29
申请号：US11461048
申请日：2006-07-31
CPC分类号： H04L7/00 , H04L7/0008
摘要： A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
摘要翻译： 数据处理系统可以包括具有输出的发起者设备，其输出单独对应于沿着信令路径的第一延迟的时钟输入引用。 示例性数据处理系统还可以包括具有输入的目标设备，其输入单独对应于沿着信令路径的第二延迟的时钟输入和在信令路径内的起始设备和目标设备之间互连的系统总线 。 示例性数据处理系统还可以包括耦合到信令路径内的系统总线的动态定时桥，其中响应于表示至少一个系统特性的控制信号，动态定时桥执行从由（i ）在信令路径内插入循环延迟，并且（ii）不在信令路径内插入循环等待时间。
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公开(公告)号：US07249223B2
公开(公告)日：2007-07-24
申请号：US10916298
申请日：2004-08-11
申请人： William C. Moyer , Craig D. Shaw
发明人： William C. Moyer , Craig D. Shaw
IPC分类号： G06F12/00
CPC分类号： G06F12/0215
摘要： A method and apparatus is provided for prefetching in a data processing system (10). The data processing system (10) has a bus master (14) and a memory controller (16) coupled to a bus (12). A memory (18) is coupled to the memory controller (16). In the data processing system (14) an address is driven onto the bus (12). Before the address is qualified, data corresponding to the address is prefetched. Prefetching the data before the address is qualified allows prefetches to be accomplished sooner.
摘要翻译： 提供了一种用于在数据处理系统（10）中预取的方法和装置。 数据处理系统（10）具有总线主机（14）和耦合到总线（12）的存储器控制器（16）。 存储器（18）耦合到存储器控制器（16）。 在数据处理系统（14）中，地址被驱动到总线（12）上。 在地址合格之前，与地址对应的数据将被预取。 在地址合格之前预取数据可以提前完成预取。
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公开(公告)号：US07080191B2
公开(公告)日：2006-07-18
申请号：US10034834
申请日：2001-12-27
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.
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公开(公告)号：US20090248935A1
公开(公告)日：2009-10-01
申请号：US12057989
申请日：2008-03-28
申请人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
发明人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
IPC分类号： G06F13/24
CPC分类号： G06F13/26
摘要： A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.
摘要翻译： 提供了一种灵活的中断控制器电路和方法，其使用中断电路（300），该中断电路（300）基于在模式控制选择器（326）中识别的系统的当前上下文复用（324）多个中断优先级寄存器（321,322） ）。 通过使用模式控制选择器（326）选择性地将不同的优先级分配耦合到优先级编码模块（330），可以以降低的等待时间来实现分配给每个中断请求的优先级的上下文敏感切换。 上下文切换可以基于OS上下文ID，电源管理模式，安全模式和其他优先级别不同的系统定义模式。 所选择的优先级信息用于提供将在数据处理系统中发生中断的中断请求信号（332）。
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8.发明授权公开(公告)号：US07434264B2
公开(公告)日：2008-10-07
申请号：US10384024
申请日：2003-03-07
CPC分类号： G06F21/85 , G06F2221/2113 , G06F2221/2141
摘要： A flexible peripheral access protection mechanism within a data processing system (10, 100). In one embodiment, each master (14, 15) within the data processing system (10) includes a corresponding privilege level modifier (70, 74) and corresponding trust attributes (71, 72, 75, 76) for particular bus access types (e.g. read and write accesses). Also, in one embodiment, each peripheral (22, 24) within the data processing system (10) includes a corresponding trust attribute (80, 84), write protect indicator (81, 85), and a privilege protect indicator (82, 86). Therefore, in one embodiment, a bus access by a bus master to a peripheral is allowed when the bus master has the appropriate privilege level and appropriate level of trust required by the peripheral (and the peripheral is not write protected, if the bus access is a write access). Also, through the use of the privilege level modifiers, a the bus master can be forced to a particular privilege level for a particular bus access.
摘要翻译： 一种在数据处理系统（10,100）内的灵活的外围设备访问保护机制。 在一个实施例中，数据处理系统（10）内的每个主机（14,15）包括用于特定总线访问类型的对应的权限级别修改器（70,74）和对应的信任属性（71,72,75,76）（例如， 读写访问）。 此外，在一个实施例中，数据处理系统（10）内的每个外围设备（22,24）包括相应的信任属性（80,84），写入保护指示符（81,85）和特权保护指示符（82,86 ）。 因此，在一个实施例中，当总线主机具有适当的特权级别和外设所需的适当的信任级别（并且外围设备不被写保护时，如果总线访问是 写访问）。 此外，通过使用特权级别修改器，可以将总线主机强制为特定总线访问的特定权限级别。
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公开(公告)号：US07793025B2
公开(公告)日：2010-09-07
申请号：US12057989
申请日：2008-03-28
申请人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
发明人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
CPC分类号： G06F13/26
摘要： A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.
摘要翻译： 提供了一种灵活的中断控制器电路和方法，其使用中断电路（300），该中断电路（300）基于在模式控制选择器（326）中识别的系统的当前上下文复用（324）多个中断优先级寄存器（321,322） ）。 通过使用模式控制选择器（326）选择性地将不同的优先级分配耦合到优先级编码模块（330），可以以降低的等待时间来实现分配给每个中断请求的优先级的上下文敏感切换。 上下文切换可以基于OS上下文ID，电源管理模式，安全模式和其他优先级别不同的系统定义模式。 所选择的优先级信息用于提供将在数据处理系统中发生中断的中断请求信号（332）。
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公开(公告)号：US06574707B2
公开(公告)日：2003-06-03
申请号：US09849704
申请日：2001-05-07
申请人： Craig D. Shaw
发明人： Craig D. Shaw
IPC分类号： G06F1200
CPC分类号： G06F12/0879 , G06F12/0859 , Y02D10/13
摘要： A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.
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