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1.发明授权公开(公告)号：US08400190B2
公开(公告)日：2013-03-19
申请号：US12565624
申请日：2009-09-23
IPC分类号： H03K3/00
CPC分类号： H03K3/00 , H03K19/0002 , H03K19/09425
摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。
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2.发明申请公开(公告)号：US20110068837A1
公开(公告)日：2011-03-24
申请号：US12565624
申请日：2009-09-23
CPC分类号： H03K3/00 , H03K19/0002 , H03K19/09425
摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。
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公开(公告)号：US20110128809A1
公开(公告)日：2011-06-02
申请号：US12769456
申请日：2010-04-28
IPC分类号： G11C8/00
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
摘要翻译： 存储器集成电路具有访问存储器集成电路的存储单元的控制电路。 控制电路响应于包括第一命令和第二命令的命令。 第一个命令指定高位地址位集合。 第二个命令指定低位地址位集合。 地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。 第一个命令和第二个命令在命令代码中有所不同。
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公开(公告)号：US08345505B2
公开(公告)日：2013-01-01
申请号：US12769456
申请日：2010-04-28
IPC分类号： G11C8/00
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
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