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1.
公开(公告)号:US20110057638A1
公开(公告)日:2011-03-10
申请号:US12751092
申请日:2010-03-31
Applicant: CHUN-MING LIN , KER CHENG LIU
Inventor: CHUN-MING LIN , KER CHENG LIU
IPC: G05F1/618
CPC classification number: H02M3/156
Abstract: A pulse width modulation regulator IC is provided for controlling a duty cycle of at least one switch to convert one input voltage signal into an output voltage. An input pin is provided for receiving an input signal different from the input voltage signal. The input signal has a lasting time substantially the same as the time that input voltage signal situated at a high level, but the waveforms of the two signals are different. The input signal is converted into a square wave signal by a conversion unit, and a PWM signal is generated by a PWM controller according to the square wave signal to control the duty cycle of the switch. Therefore, the input pin can be saved by adjusting an internal or external circuit of the IC for the usage of the different kinds of input signals without increasing the number of input pins of the IC.
Abstract translation: 提供脉宽调制调节器IC用于控制至少一个开关的占空比以将一个输入电压信号转换为输出电压。 输入引脚用于接收与输入电压信号不同的输入信号。 输入信号的持续时间与输入电压信号位于高电平的时间基本相同,但两个信号的波形不同。 输入信号由转换单元转换成方波信号,根据方波信号由PWM控制器生成PWM信号,以控制开关的占空比。 因此,可以通过调整IC的内部或外部电路来保存输入引脚,以便使用不同种类的输入信号,而不增加IC的输入引脚数量。
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公开(公告)号:US20240413048A1
公开(公告)日:2024-12-12
申请号:US18779081
申请日:2024-07-22
Applicant: CHUN-MING LIN
Inventor: CHUN-MING LIN
IPC: H01L23/373 , H01L23/00 , H01L23/31 , H01L23/367 , H01L25/065
Abstract: The present disclosure provides a package structure. The package structure includes: a first die having a first front surface and a first back surface opposite to the first front surface; a second die having a second front surface and a second back surface opposite to the second front surface, wherein the first back surface faces the first front surface; and a first thermal management structure over the first back surface. The first thermal management structure includes a first copper-phosphorous alloy layer thermally coupled to the first back surface.
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3.
公开(公告)号:US20230298991A1
公开(公告)日:2023-09-21
申请号:US17697937
申请日:2022-03-18
Applicant: CHUN-MING LIN
Inventor: CHUN-MING LIN
IPC: H01L23/498 , H01L21/48 , C25D3/38 , C25D7/12
CPC classification number: H01L23/49866 , H01L23/49822 , H01L23/49827 , H01L21/4857 , C25D3/38 , C25D7/12
Abstract: The present disclosure provides a multilayer wiring structure, including a plurality of dielectric layers, a plurality of conductive wiring layers interleaved with the plurality of dielectric layers, wherein the plurality of conductive wiring layers includes copper-phosphorous alloys (such as Cu3P).
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公开(公告)号:US20240413047A1
公开(公告)日:2024-12-12
申请号:US18779080
申请日:2024-07-22
Applicant: CHUN-MING LIN
Inventor: CHUN-MING LIN
IPC: H01L23/373 , H01L23/00 , H01L23/31 , H01L23/367 , H01L25/065
Abstract: The present disclosure provides a package structure. The package structure includes: a first die having a front surface and a back surface opposite to the front surface; and a first thermal management structure over the back surface. The first thermal management structure includes: a first copper-phosphorous alloy layer thermally coupled to and covering an entirety of the back surface of the first die.
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5.
公开(公告)号:US20240063110A1
公开(公告)日:2024-02-22
申请号:US18492816
申请日:2023-10-24
Applicant: CHUN-MING LIN
Inventor: CHUN-MING LIN
CPC classification number: H01L23/49866 , H01L23/49822 , C25D7/12 , H01L21/4857 , C25D3/38 , H01L23/49827 , H05K1/112 , H05K1/09 , H05K1/115 , H05K2201/0364 , H05K2201/095 , H05K2201/09509 , H05K1/18
Abstract: The present disclosure provides a method for forming a multilayer wiring structure, which includes: forming a patterned copper-phosphorous alloy layer over a carrier by performing a plating operation, and forming a dielectric layer over the patterned copper-phosphorous alloy layer. The forming the patterned copper-phosphorous alloy layer includes providing a plating solution having a copper source and a phosphorous source.
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