公开(公告)号：US20240334617A1

公开(公告)日：2024-10-03

申请号：US18609546

申请日：2024-03-19

Applicant: AT&S Austria Technologie & Systemtechnik AG

Inventor： Hans PARK ,  Jeesoo MOK

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K3/4673 ,  H05K1/0298 ,  H05K3/4038 ,  H05K2201/095 ,  H05K2203/0147

Abstract: A component carrier and a method of manufacturing the component carrier are presented. The component carrier includes a stack having a stack with: i) at least two electrically insulating layer structures; ii) a first electrically conductive layer structure, including a first line spacing, and at least one second electrically conductive layer structure, having a second line spacing embedded in and/or provided on one of the at least two electrically insulating layer structures, respectively; iii) at least one third electrically conductive layer structure, having a third line spacing, provided on and/or in one of the at least two electrically insulating layer structures, wherein the first line spacing and the second line spacing is larger than the third line spacing, wherein the third electrically conductive layer structure is arranged between the first electrically conductive layer structure and the second electrically conductive layer structure in the stacking direction of the stack; and iv) an electrically conductive connection that electrically connects the first electrically conductive layer structure and the second electrically conductive layer structure in the stacking direction, wherein the electrically conductive connection passes through the third electrically conductive layer structure at a connection layer structure.

公开(公告)号：US20240107684A1

公开(公告)日：2024-03-28

申请号：US18475276

申请日：2023-09-27

Applicant: IBIDEN CO., LTD.

Inventor： Jun SAKAI ,  Takuya INISHI ,  Susumu KAGOHASHI

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/16

CPC classification number: H05K3/4608 ,  H05K1/115 ,  H05K3/16 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/095

Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed and electrolytic plating layers and connecting the first and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second and third portions, and the insulating layer includes resin and inorganic particles including first particles forming the inner wall surface and second particles embedded in the insulating layer and having shapes different from shapes of the first particles.

公开(公告)号：US11800249B2

公开(公告)日：2023-10-24

申请号：US17646751

申请日：2022-01-03

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Yuta Momiuchi ,  Yuji Takaoka

IPC: H04N25/70 ,  H01L27/146 ,  H04N23/00 ,  H04N23/54 ,  H04N23/57 ,  H04N25/44 ,  G03B17/02 ,  H05K1/18 ,  H05K3/10

CPC classification number: H04N25/70 ,  G03B17/02 ,  H01L27/146 ,  H01L27/14618 ,  H01L27/14636 ,  H04N23/00 ,  H04N23/54 ,  H04N23/57 ,  H04N25/44 ,  H05K1/185 ,  H05K3/103 ,  H05K2201/095 ,  H05K2201/09118

Abstract: A rewiring region 22 is provided in a region other than a pixel region 21 on a front face (pixel formation surface) FA of an imaging element 20. A mold part 30 is formed around the imaging element 20 other than on the front face FA. Rewiring layers 41b, 42b, and 43b that connect an external terminal and a pad 23 provided in the rewiring region 22 are formed via insulating layers 41a, 42a, and 43a on a side of the pixel formation surface of the imaging element 20 and the mold part 30. Therefore, connection to a substrate can be made possible even if the spacing between the pads is narrowed, a mounting surface of an imaging device 10 is also on the side of the pixel formation surface, and reduction in size and height can be achieved.

公开(公告)号：US11770902B2

公开(公告)日：2023-09-26

申请号：US17498767

申请日：2021-10-12

Applicant: WUXI SHENNAN CIRCUITS CO., LTD.

Inventor： Yunfeng Jiao ,  Lei You ,  Zhicheng Yang ,  Lihua Zhang ,  Hua Miao

IPC: H05K1/02 ,  H05K3/32 ,  H05K1/05

CPC classification number: H05K3/32 ,  H05K1/0296 ,  H05K1/05 ,  H05K2201/03 ,  H05K2201/095

Abstract: A circuit board, a preparation method thereof, and an electronic device are provided. The circuit board includes: a substrate, defining a first through-hole; a metal block, embedded in the first through-hole and fixedly connected to the substrate; a conductive line layer, arranged on at least one side surface of the substrate; wherein the conductive line layer partially covers an opening of the first through-hole on a corresponding side surface of the substrate; and a conductive channel, penetrating the conductive line layer and the metal block in turn. The conductive channel comprises a second through-hole and a conductive medium plated on a wall of the second through-hole; an end of the conductive medium is connected to the conductive line layer, and another end of the conductive medium is connected to the metal block.

公开(公告)号：US20230262880A1

公开(公告)日：2023-08-17

申请号：US18162713

申请日：2023-02-01

Applicant: Unimicron Technology Corp.

Inventor： Chih-Chiang Lu ,  Jun-Rui Huang ,  Ming-Hao Wu ,  Tung-Chang Lin

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/025 ,  H05K1/112 ,  H05K1/0216 ,  H05K2201/095

Abstract: Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.

公开(公告)号：US20190246496A1

公开(公告)日：2019-08-08

申请号：US16269194

申请日：2019-02-06

Applicant: IBIDEN CO., LTD.

Inventor： Youhong WU

IPC: H05K1/02 ,  H01L23/00 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L24/11 ,  H01L24/14 ,  H05K3/4644 ,  H05K2201/095

Abstract: A printed wiring board includes a base insulating layer, a conductor layer including first and second pads, a solder resist layer covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump including base plating layer in the first opening and top plating layer on the first base layer, and a second bump including base plating layer in the second opening and top plating layer on the base layer. The second opening has smaller diameter than the first opening, and the second bump has smaller diameter than the first bump. The first base layer has flat upper surface or first recess having depth of 20 μm or less in upper central portion. The second base layer has flat upper surface, raised portion in upper central portion, or second recess shallower than the first recess in the upper central portion.

公开(公告)号：US20180287302A1

公开(公告)日：2018-10-04

申请号：US15916505

申请日：2018-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Min-Seok Kim ,  Sigwan Kim ,  Jung-Woo Kim

IPC: H01R13/6471 ,  H05K1/02 ,  H01R12/72 ,  H01R13/6466 ,  H01R13/66

CPC classification number: H01R13/6471 ,  H01R12/721 ,  H01R13/6466 ,  H01R13/6691 ,  H01R2201/16 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/095 ,  H05K2201/10189

Abstract: An electronic device according to an example embodiment includes: a substrate; and a connector including a plurality of terminals disposed on a first area of the substrate, wherein the substrate includes: a first layer including signal lines connected to the plurality of terminals and a dielectric material disposed between the signal lines; a second layer disposed on the first layer, and including a first ground electrically connected with the connector and a second ground physically isolated from the first ground; a third conductive layer disposed on the second layer, and electrically connected with the second ground; and a fourth layer having a nonconductive material disposed on an area corresponding to the first area between the second layer and the third conductive layer.

公开(公告)号：US20180160525A1

公开(公告)日：2018-06-07

申请号：US15701625

申请日：2017-09-12

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Infrastructure Systems & Solutions Corporation

Inventor： Yoshiaki SATAKE ,  Shinji TAMAI

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/0209 ,  H01L23/552 ,  H01L2924/3025 ,  H05K1/0204 ,  H05K1/0233 ,  H05K3/0061 ,  H05K3/281 ,  H05K3/284 ,  H05K3/3415 ,  H05K3/3426 ,  H05K3/429 ,  H05K7/205 ,  H05K2201/0215 ,  H05K2201/066 ,  H05K2201/095 ,  H05K2201/09581 ,  H05K2201/09872 ,  H05K2201/10689 ,  H05K2203/1311 ,  H05K2203/1316 ,  H05K2203/1322 ,  H05K2203/1438

Abstract: A circuit board device of the embodiment includes: a mount board having an electronic component and a printed circuit board having at least one surface where the electronic component is mounted; a heat path arranged to a position facing the mount surface of the mount board, a sheet arranged on the mount surface, and a resin portion arranged between the sheet and the heat path. A cavity surrounded by the sheet and the mount surface is formed in a step portion between the electronic component and the printed circuit board.

公开(公告)号：US20170064821A1

公开(公告)日：2017-03-02

申请号：US14840979

申请日：2015-08-31

Applicant: Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K3/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

Abstract translation: 一些示例形式涉及电子包装。 电子封装包括第一电介质层，其包括形成在第一电介质层的表面上的电迹线和在第一电介质层的表面上的第二电介质层。 第二电介质层包括开口。 电迹线在开口内。 电子封装包括电互连，其填充开口并且在第二电介质层的上表面上方延伸，使得电互连电连接到第一电介质层上的电迹线。

公开(公告)号：US09414497B2

公开(公告)日：2016-08-09

申请号：US14815184

申请日：2015-07-31

Applicant: Cisco Technology, Inc.

Inventor： Jovica Savic ,  Zhiping Yang ,  Jie Xue ,  Li Li

IPC: H01L29/06 ,  H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H01L23/24 ,  H01L23/31

CPC classification number: H05K1/183 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/095 ,  H05K2201/10492 ,  H05K2201/10507 ,  H01L2924/00

Abstract: An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

Abstract translation: 一种装置包括形成在支撑结构中的空腔，所述支撑结构可操作以支撑半导体器件。 电路元件设置在支撑结构中的空腔中，并且支撑结构中的空腔填充有不导电的填充材料，以便至少部分地围绕电路元件与非导电填充材料。 半导体器件电连接到电路元件。 在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。