公开(公告)号：US20150316517A1

公开(公告)日：2015-11-05

申请号：US14335175

申请日：2014-07-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Eric OLLIER ,  Carine MARCOUX

IPC: G01N30/60 ,  B01D53/02 ,  B81C1/00 ,  G01N30/64

CPC classification number: G01N30/6095 ,  B01D53/02 ,  B81B2201/058 ,  B81C1/00119 ,  B81C1/00269 ,  B81C2203/0172 ,  G01N30/64 ,  H01L2924/1461

Abstract: Device including a substrate including at least one microelectronic and/or nanoelectronic structure (NEMS) having a sensitive portion and a fluid channel. The fluid channel includes two lateral walls, an upper wall connecting the two lateral walls, a lower wall formed by the substrate, and at least two openings in order to provide a circulation in the fluid channel, with the openings being defined between the two lateral walls, with the structure being located inside the fluid channel. Electrical connection lines extend between the structure and the outside of the fluid channel, with the connection lines being carried out on the substrate and passing under the lateral walls. The device also includes an intermediate layer having a planar face in contact with base faces of said lateral walls. The connection lines are at least partially covered by the intermediate layer at least immediately above base faces of the lateral walls. The lateral walls are made sealingly integral on the substrate by a sealing layer on the intermediate layer.

Abstract translation: 包括具有至少一个具有敏感部分和流体通道的微电子和/或纳米电子结构（NEMS）的衬底的器件。 流体通道包括两个侧壁，连接两个侧壁的上壁，由基底形成的下壁和至少两个开口，以便在流体通道中提供循环，其中开口限定在两个横向 其结构位于流体通道内。 电气连接线在流体通道的结构和外部之间延伸，连接线在基板上进行并在侧壁之下通过。 该装置还包括具有与所述侧壁的基面相接触的平面的中间层。 连接线至少部分地被中间层覆盖，至少紧邻侧壁的基面上方。 侧壁通过中间层上的密封层密封地整合在基底上。

公开(公告)号：US20150021720A1

公开(公告)日：2015-01-22

申请号：US14336351

申请日：2014-07-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Eric OLLIER ,  Carine MARCOUX

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0292 ,  B81B2201/058 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/00269 ,  B81C1/00309 ,  B81C2203/0118 ,  G01N30/6095

Abstract: A device comprising a substrate comprising at least one microelectronic and/or nanoelectronic structure comprising at least one sensitive portion and one fluid channel (2) defined between said substrate and a cap (6), where said fluid channel (2) comprises at least two apertures to provide a flow in said channel, where said microelectronic and/or nanoelectronic structure is located within the fluid channel, where said cap is assembled with the substrate at an assembly interface, where said device comprises electrical connections between said microelectronic and/or nanoelectronic structure and the exterior of the fluid channel (2), where said electrical connections (8) are formed by vias made through the substrate (4) directly below the microelectronic and/or nanoelectronic structure, and in electrical contact with said microelectronic and/or nanoelectronic structure.

Abstract translation: 一种包括衬底的器件，包括至少一个微电子和/或纳米电子结构，所述微电子和/或纳米电子结构包括限定在所述衬底和帽（6）之间的至少一个敏感部分和一个流体通道（2），其中所述流体通道（2）包括至少两个 孔，以在所述通道中提供流动，其中所述微电子和/或纳米电子结构位于流体通道内，其中所述盖与基板组装在组装界面处，其中所述装置包括所述微电子和/或纳米电子 结构和流体通道（2）的外部，其中所述电连接（8）由通过直接在微电子和/或纳米电子结构下面的基板（4）制成的通孔形成，并且与所述微电子和/或 纳米电子结构。

公开(公告)号：US20150329986A1

公开(公告)日：2015-11-19

申请号：US14514703

申请日：2014-10-15

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Eric OLLIER ,  Frederic-Xavier Gaillard ,  Carine Marcoux

IPC: C25F3/12 ,  C25F3/02

Abstract: A process for making at least one porous area (ZP) of a microelectronic structure in at least one part of an conducting active layer (6), the active layer (6) forming a front face of a stack, the stack comprising a back face (2) of conducting material and an insulating layer (4) interposed between the active layer (6) and the back face (2), said process comprising the steps of:a) making at least one contact pad (14) between the back face (2) and the active layer (6) through the insulation layer (2),b) placing the stack into an electrochemical bath,c) applying an electrical current between the back face (2) and the active layer (6) through the contact pad (14) causing porosification of an area (ZP) of the active layer (6) in the vicinity of the contact pad (14),d) forming the microelectronic structure.

Abstract translation: 一种用于在导电有源层（6）的至少一部分中制造微电子结构的至少一个多孔区域（ZP）的方法，所述有源层（6）形成堆叠的前表面，所述堆叠包括背面 （2）和介于有源层（6）和背面（2）之间的导电材料和绝缘层（4），所述方法包括以下步骤：a）在背面之间制造至少一个接触焊盘（14） （2）和有源层（6）通过绝缘层（2），b）将叠层放入电化学浴中，c）在背面（2）和有源层（6）之间通过 所述接触焊盘（14）引起所述有源层（6）在所述接触焊盘（14）附近的区域（ZP）的开孔，d）形成所述微电子结构。

公开(公告)号：US20150274516A1

公开(公告)日：2015-10-01

申请号：US14182659

申请日：2014-02-18

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Eric OLLIER

IPC: B81C1/00

CPC classification number: B81C1/00515 ,  B81C1/00206 ,  B81C1/00412 ,  B81C1/00626 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/038

Abstract: Process for fabrication of a micromechanical and/or nanomechanical structure comprising the following steps, starting from an element comprising a support substrate and a sacrificial layer: a) formation of a first layer, at least part of which is porous, b) formation on the first layer of a layer made of one (or several) materials providing the mechanical properties of the structure, called the intermediate layer, c) formation on the intermediate layer of a second layer, at least part of which is porous, d) formation of said structure in the stack composed of the first layer, the intermediate layer and the second layer, e) release of said structure by at least partial removal of the sacrificial layer.

Abstract translation: 制造微机械和/或纳米机械结构的方法，包括以下步骤：从包括支撑基底和牺牲层的元件开始：a）形成第一层，其中至少一部分是多孔的，b）在 第一层由一种（或多种）材料制成，提供称为中间层的结构的机械性能，c）在第二层的中间层上形成，其中至少一部分是多孔的，d）形成 由第一层，中间层和第二层构成的堆叠中的所述结构，e）通过至少部分去除牺牲层来释放所述结构。