公开(公告)号：US20160342592A1

公开(公告)日：2016-11-24

申请号：US15114514

申请日：2015-02-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Jerome Belledent

IPC: G06F17/30 ,  G06K9/00 ,  G06K9/62 ,  G06F17/14 ,  G06T7/00

CPC classification number: G06F17/3028 ,  G06F17/141 ,  G06F19/707 ,  G06K9/00147 ,  G06K9/48 ,  G06K9/6202 ,  G06T7/001

Abstract: A method for determining a self-assembly pattern of a block copolymer confined inside a closed outline called the guiding outline, comprises the following steps, which are implemented by computer: a) choosing in a database a closed outline called the reference outline that is similar to the guiding outline, a self-assembly pattern of the block copolymer, called the reference pattern, being associated with the reference outline; b) applying a geometric transformation to a plurality of points of said reference pattern in order to convert them to respective points called image points of the self-assembly pattern to be determined. A computer program product for implementing such a method is provided.

Abstract translation: 用于确定被称为引导轮廓的闭合轮廓内的嵌段共聚物的自组装图案的方法包括以下步骤，其由计算机实现：a）在数据库中选择称为参考轮廓的封闭轮廓，其类似于 对于引导轮廓，称为参考图案的嵌段共聚物的自组装图案与参考轮廓相关联; b）将几何变换应用于所述参考图案的多个点，以便将它们转换成被确定的称为自组装图案的图像点的各个点。 提供了一种用于实现这种方法的计算机程序产品。

公开(公告)号：US20140172386A1

公开(公告)日：2014-06-19

申请号：US14105648

申请日：2013-12-13

Applicant: Aselta Nanographics ,  Commissariat A L'Energie Atomique Et Aux Energies Alternatives

Inventor： Jerome Belledent

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G03F7/705 ,  G03F7/70558 ,  G03F7/70625 ,  H01J2237/31793

Abstract: Method for simulating shot-noise effects in a particle-beam lithography process, and especially an e-beam lithography process, the process including depositing particles on the surface of a sample in a preset pattern by a beam of the particles, the pattern being subdivided into pixels and a nominal dose of particles being associated with each of the pixels, wherein the process includes the calculation of a map σd of standard deviation in the normalized dose actually deposited in each of the pixels, the map of standard deviation being calculated from a map M0 of the nominal dose associated with each pixel and a point spread function PSF characterizing the process; the method being implemented by computer. Computer program product for implementing and computer programmed to implement such a method. Particle-beam lithography process, and especially an e-beam lithography process, having a prior operation of simulating shot-noise effects using such a method.

Abstract translation: 用于模拟粒子束光刻工艺中的散粒噪声效应的方法，特别是电子束光刻工艺，该方法包括通过颗粒束将预定图案中的颗粒沉积在样品的表面上，该图案被细分 到像素中并且与每个像素相关联的标称剂量的颗粒，其中该过程包括计算实际沉积在每个像素中的标准化剂量中的标准偏差的映射和标准差，计算标准偏差的映射 从与每个像素相关联的标称剂量的映射M0和表征该过程的点扩散函数PSF; 该方法由计算机实现。 计算机程序产品实现和计算机程序化实现这种方法。 粒子束光刻工艺，特别是电子束光刻工艺，具有使用这种方法模拟散粒噪声效应的先前操作。

公开(公告)号：US09558957B2

公开(公告)日：2017-01-31

申请号：US13894890

申请日：2013-05-15

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Francois Andrieu ,  Sebastien Barnola ,  Jerome Belledent

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431

Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).

Abstract translation: 基板依次设置有支撑体（7），电绝缘层（8）和半导体材料层（2）。 第一保护掩模（1）完全覆盖半导体材料层的第二区域（B）并且留下未覆盖的半导体材料层的第一区域（A）。 第二蚀刻掩模（3）部分地覆盖第一区域（A）并且至少部分地覆盖第二区域（B），以便限定和分离第一区域和第二区域。 在第二蚀刻掩模（3）的侧表面上形成横向间隔件，以形成第三蚀刻掩模。 通过第三蚀刻掩模蚀刻半导体材料层（2），以在第一区域（A）中形成由半导体材料制成的图案，第一蚀刻掩模（3）保护第二区域 B）。