公开(公告)号：US09698250B2

公开(公告)日：2017-07-04

申请号：US14855807

申请日：2015-09-16

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Nicolas Posseme ,  Christian Arvet ,  Sebastien Barnola

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/2658 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/785

Abstract: A method for etching a dielectric layer located on the surface of a three-dimensional structure formed on a face of a substrate oriented along a plane of a substrate, which includes a step of implanting ions so as to directionally create a top layer in the dielectric layer. Such top layer is thus not formed everywhere. Then, the layer in question is removed, except on the predefined zones, such as flanks of a transistor gate. A selective etching of the dielectric layer is executed relative to the material of the residual part of the top layer and relative to the material of the face of the substrate.

公开(公告)号：US09953807B2

公开(公告)日：2018-04-24

申请号：US15612680

申请日：2017-06-02

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stefan Landis ,  Sebastien Barnola ,  Thibaut David ,  Lamia Nouri ,  Nicolas Posseme

IPC: H01J37/317 ,  H01J37/305

CPC classification number: H01J37/3175 ,  B82Y40/00 ,  H01J37/3053 ,  H01J37/3171 ,  H01J2237/08 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30608 ,  H01L31/02363 ,  H01L31/18 ,  H01L31/1804 ,  H01L33/005 ,  H01L33/20 ,  Y02E10/547

Abstract: A method for forming reliefs on the surface of a substrate, including a first implantation of ions in the substrate according to a first direction; a second implantation of ions in the substrate according to a second direction that is different from the first direction; at least one of the first and second implantations is carried out through at least one mask having at least one pattern; an etching of areas of the substrate having received by implantation a dose greater than or equal to a threshold, selectively to the areas of the substrate that have not received via implantation a dose greater than said threshold; the parameters of the first and second implantations being adjusted in such a way that only areas of the substrate that have been implanted both during the first implantation and during the second implantation receive a dose greater than or equal to said threshold.

公开(公告)号：US09934973B2

公开(公告)日：2018-04-03

申请号：US15538564

申请日：2015-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stefan Landis ,  Nicolas Posseme ,  Sebastien Barnola ,  Thibaut David ,  Lamia Nouri

IPC: H01L21/266 ,  C23C14/48 ,  C23C14/04 ,  H01L21/3065 ,  H01L21/306 ,  B81C1/00 ,  H01L33/00 ,  H01L33/22 ,  H01L31/18 ,  H01L31/0392 ,  G03F7/00

CPC classification number: H01L21/266 ,  B81C1/00103 ,  B81C1/0046 ,  B81C1/00587 ,  B81C2201/0136 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/042 ,  C23C14/48 ,  G03F7/0002 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L31/02363 ,  H01L31/0392 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/20 ,  H01L33/22 ,  Y02E10/50

Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patterns.

公开(公告)号：US10573529B2

公开(公告)日：2020-02-25

申请号：US16233948

申请日：2018-12-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Posseme ,  Sebastien Barnola

IPC: H01L21/311 ,  H01L29/66

Abstract: A method for etching a dielectric layer covering at least one top and at least one flank of a semi-conductive material-based structure is provided, including a plurality of sequences, each including successive steps of: a first etching of the layer by plasma using a chemistry including at least a first fluorine-based compound and a second compound chosen from SiwCl(2w+2) and SiwF(2w+2), w, x, y, and z being whole numbers, and oxygen, the first etching: interrupting before complete consumption of the dielectric layer thickness on the flank and after complete consumption of the thickness on the top, and forming a first protective layer on the top and a second protective layer on the flank; and a second etching fully removing the second layer while conserving a portion of the first layer thickness, each sequence being repeated until complete removal of the dielectric layer on the flank.

公开(公告)号：US10347545B2

公开(公告)日：2019-07-09

申请号：US15599944

申请日：2017-05-19

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Laurent Grenouillet ,  Sebastien Barnola ,  Marie-Anne Jaud ,  Jerome Mazurier ,  Nicolas Posseme

IPC: H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.

公开(公告)号：US09558957B2

公开(公告)日：2017-01-31

申请号：US13894890

申请日：2013-05-15

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Francois Andrieu ,  Sebastien Barnola ,  Jerome Belledent

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431

Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).

Abstract translation: 基板依次设置有支撑体（7），电绝缘层（8）和半导体材料层（2）。 第一保护掩模（1）完全覆盖半导体材料层的第二区域（B）并且留下未覆盖的半导体材料层的第一区域（A）。 第二蚀刻掩模（3）部分地覆盖第一区域（A）并且至少部分地覆盖第二区域（B），以便限定和分离第一区域和第二区域。 在第二蚀刻掩模（3）的侧表面上形成横向间隔件，以形成第三蚀刻掩模。 通过第三蚀刻掩模蚀刻半导体材料层（2），以在第一区域（A）中形成由半导体材料制成的图案，第一蚀刻掩模（3）保护第二区域 B）。

公开(公告)号：US09543409B2

公开(公告)日：2017-01-10

申请号：US14855834

申请日：2015-09-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Christian Arvet ,  Sebastien Barnola ,  Sebastien Lagrasta ,  Nicolas Posseme

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/6656 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628

Abstract: The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.

Abstract translation: 在晶体管栅极的侧面制造间隔物，包括形成覆盖栅极的介电层和围绕栅极的半导体材料层的外围区域的步骤，包括形成覆盖栅极和外围区域的表面层; 部分去除表层，构造成在外围区域完全除去表层，同时在侧面保留表层的残留部分; 并且相对于表层的残余部分的材料和相对于半导体材料的材料的电介质层的选择性蚀刻。