公开(公告)号：US11239374B2

公开(公告)日：2022-02-01

申请号：US16697558

申请日：2019-11-27

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Sylvain Barraud ,  Joris Lacord

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.

公开(公告)号：US10914703B2

公开(公告)日：2021-02-09

申请号：US15827206

申请日：2017-11-30

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Olivier Rozeau ,  Marie-Anne Jaud ,  Joris Lacord ,  Sébastien Martinie ,  Thierry Poiroux

IPC分类号： G01N27/22 ,  G01B21/08 ,  G01B15/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  G01N23/2251 ,  B82Y10/00 ,  G01R29/24 ,  B82Y35/00 ,  B82Y30/00 ,  G01R31/26

摘要： Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW, width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW, thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW, corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ϕT given by ϕT=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.