公开(公告)号：US09235668B1

公开(公告)日：2016-01-12

申请号：US14332907

申请日：2014-07-16

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Thierry Poiroux ,  Marie-Anne Jaud ,  Sebastien Martinie ,  Olivier Rozeau

IPC分类号： G06F17/50 ,  H01L29/786

CPC分类号： G06F17/5036 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78696

摘要： A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.

摘要翻译： 一种计算机实现的方法，用于计算包括具有第一和第二栅极接口的薄体的双栅极晶体管的第一栅极的电荷密度q1，所述方法包括使用物理处理器确定初始估计值q1， 第一栅极的电荷密度; 使用物理处理器，基于能够被第一门的电荷密度q1的正确值无效的函数fzero（q1）的泰勒展开来执行初始估计的至少两个基本校正。

公开(公告)号：US10347545B2

公开(公告)日：2019-07-09

申请号：US15599944

申请日：2017-05-19

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Laurent Grenouillet ,  Sebastien Barnola ,  Marie-Anne Jaud ,  Jerome Mazurier ,  Nicolas Posseme

IPC分类号： H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

摘要： There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.

公开(公告)号：US10914703B2

公开(公告)日：2021-02-09

申请号：US15827206

申请日：2017-11-30

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Olivier Rozeau ,  Marie-Anne Jaud ,  Joris Lacord ,  Sébastien Martinie ,  Thierry Poiroux

IPC分类号： G01N27/22 ,  G01B21/08 ,  G01B15/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  G01N23/2251 ,  B82Y10/00 ,  G01R29/24 ,  B82Y35/00 ,  B82Y30/00 ,  G01R31/26

摘要： Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW, width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW, thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW, corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ϕT given by ϕT=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.