公开(公告)号：US20170352722A1

公开(公告)日：2017-12-07

申请号：US15539554

申请日：2016-09-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong ZHONG ,  Xiaoshe DENG ,  Dongfei ZHOU

IPC: H01L29/06 ,  H01L29/861 ,  H01L21/768 ,  H01L21/02 ,  H01L21/04 ,  H02M3/158 ,  H01L21/78

Abstract: A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type (100), an epitaxial layer of a first conductivity type (200) formed on the substrate of the first conductivity type (100), wherein the epitaxial layer of the first conductivity type (200) defines a plurality of trenches (310) thereon; a filling structure (300) comprising an insulating material formed on the inner surface of the trench (310) and a conductive material filled in the trench (310); a doped region of a second conductivity type (400) formed in the surface of the epitaxial layer of the first conductivity type (200) located between the filling structures (300); an upper electrode (600) formed on a surface of the epitaxial layer of the first conductivity type (200); a guard ring (700) formed in the surface layer of the epitaxial layer of the first conductivity type (200); and a guard layer (800).

公开(公告)号：US20180102406A1

公开(公告)日：2018-04-12

申请号：US15840791

申请日：2017-12-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong ZHONG ,  Dongfei ZHOU ,  Xiaoshe DENG ,  Genyi WANG

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/761 ,  H01L29/04 ,  H01L29/161 ,  H01L29/66 ,  H01L29/10 ,  H01L29/739 ,  H01L29/20

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

公开(公告)号：US20160380072A1

公开(公告)日：2016-12-29

申请号：US14902517

申请日：2014-07-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong ZHONG ,  Xiaoshe DENG ,  Genyi WANG ,  Dongfei ZHOU

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/265 ,  H01L29/739 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66333 ,  H01L21/02233 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7395

Abstract: An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

Abstract translation: 一种绝缘栅双极晶体管及其制造方法。 绝缘栅双极晶体管包括具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括原始单元区域 （2）和位于原始单元区域外部的端子保护区域（4）; 形成在半导体衬底（1）的第一主表面侧的第一导电类型的第一半导体层（5），其中第一半导体层（5）的掺杂浓度高于 半导体衬底（1）; 以及绝缘栅晶体管单元，其形成在原电池区域中的第一半导体层（5）的第一主表面侧，其中绝缘栅晶体管单元导通，形成第一导电类型的沟道。 与现有技术相比，本发明不仅可以提高绝缘栅双极晶体管的耐电压可靠性，而且可以降低绝缘栅双极晶体管的正向导通电压降。