公开(公告)号：US11462628B2

公开(公告)日：2022-10-04

申请号：US16771168

申请日：2018-11-13

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L31/062 ,  H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

公开(公告)号：US11552164B2

公开(公告)日：2023-01-10

申请号：US17265565

申请日：2019-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L21/22 ,  H01L21/26 ,  H01L29/06 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

公开(公告)号：US11158737B2

公开(公告)日：2021-10-26

申请号：US16644856

申请日：2018-08-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun ,  Hongfeng Jin

IPC: H01L29/78 ,  H01L29/66

Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.

公开(公告)号：US11923453B2

公开(公告)日：2024-03-05

申请号：US17631287

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Chunxu Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L29/0611 ,  H01L29/401 ,  H01L29/404 ,  H01L29/66681

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

公开(公告)号：US10811520B2

公开(公告)日：2020-10-20

申请号：US16462432

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall; removing the second dielectric layer (240) in the source region side wall and retaining the first dielectric layer (230) therein.

公开(公告)号：US12205996B2

公开(公告)日：2025-01-21

申请号：US17766406

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.

公开(公告)号：US11588049B2

公开(公告)日：2023-02-21

申请号：US17262882

申请日：2019-07-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device and method for manufacturing same. The semiconductor device comprises: a drift region (120); an isolation structure (130) contacting the drift region (120), the isolation structure (130) comprising a first isolation layer (132), a hole etch stop layer (134) on the first isolation layer (132), and a second isolation layer (136) on the hole etch stop layer (134); and a hole field plate (180) provided above the hole etch stop layer (134) and contacting the hole etch stop layer (134).

公开(公告)号：US20210242305A1

公开(公告)日：2021-08-05

申请号：US17265565

申请日：2019-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

公开(公告)号：US20210234041A1

公开(公告)日：2021-07-29

申请号：US17262882

申请日：2019-07-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device and method for manufacturing same. The semiconductor device comprises: a drift region (120); an isolation structure (130) contacting the drift region (120), the isolation structure (130) comprising a first isolation layer (132), a hole etch stop layer (134) on the first isolation layer (132), and a second isolation layer (136) on the hole etch stop layer (134); and a hole field plate (180) provided above the hole etch stop layer (134) and contacting the hole etch stop layer (134).