公开(公告)号：US20230215503A1

公开(公告)日：2023-07-06

申请号：US17928333

申请日：2021-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Ming GU ,  Hao WANG ,  Shuming GUO ,  Youhui LI ,  Bin CHEN ,  Yongqiang HU

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.