公开(公告)号：US20230154549A1

公开(公告)日：2023-05-18

申请号：US17916927

申请日：2021-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Bin CHEN ,  Youhui LI ,  Ming GU ,  Xinmiao ZHAO ,  Hao WANG ,  Shuming GUO ,  Zongchuan WANG ,  Nan ZHANG

IPC: G11C16/30 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/26

Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

公开(公告)号：US20230215503A1

公开(公告)日：2023-07-06

申请号：US17928333

申请日：2021-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Ming GU ,  Hao WANG ,  Shuming GUO ,  Youhui LI ,  Bin CHEN ,  Yongqiang HU

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.

公开(公告)号：US20230095590A1

公开(公告)日：2023-03-30

申请号：US17799459

申请日：2020-12-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Youhui LI ,  Lijuan ZHU

IPC: G05F3/24 ,  G11C16/30

Abstract: A bias current generation circuit and a flash memory. The bias current generation circuit includes a voltage source, a switching circuit and a current generation circuit. The voltage source is configured to provide a voltage for generating a bias current. An input terminal of the switching circuit is connected to the voltage source, a control terminal of the switching circuit is configured to receive a control signal. The current generation circuit includes a first MOS transistor and a second MOS transistor, an input terminal and a control terminal of the first MOS transistor are connected to an output terminal of the switching circuit, an output terminal of the first MOS transistor is connected to an input terminal and a control terminal of the second MOS transistor, and an output terminal of the second MOS transistor is grounded.