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公开(公告)号：US20220077865A1
公开(公告)日：2022-03-10
申请号：US17419548
申请日：2019-12-23
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Abstract: An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.
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公开(公告)号：US20230154549A1
公开(公告)日：2023-05-18
申请号：US17916927
申请日：2021-04-28
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Bin CHEN , Youhui LI , Ming GU , Xinmiao ZHAO , Hao WANG , Shuming GUO , Zongchuan WANG , Nan ZHANG
Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.
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公开(公告)号：US20230067583A1
公开(公告)日：2023-03-02
申请号：US17796952
申请日：2021-05-27
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
IPC: G01J5/12
Abstract: An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.
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公开(公告)号：US20200343810A1
公开(公告)日：2020-10-29
申请号：US16959015
申请日：2018-12-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
Inventor： Shen XU , Minggang CHEN , Hao WANG , Jinyu XIAO , Wei SU , Weifeng SUN , Longxing SHI
Abstract: An automatic dead zone time optimization system in a primary-side regulation flyback power supply CCM mode, comprising a closed loop formed by a control system, consisting of a single output DAC midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a PWM driving module, and a controlled synchronous rectification primary-side regulation flyback converter. By means of a DAC Sampling mechanism, a primary-side current is sampled to calculate a secondary-side average current, so as to obtain a primary-side average current Imid_p and a secondary-side average current Is(tmid) in the case of CCM; a secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time td; and finally, the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time td.
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Patent Agency Ranking
5.发明申请公开(公告)号：US20200336070A1
公开(公告)日：2020-10-22
申请号：US16959001
申请日：2018-12-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
Inventor： Weifeng SUN , Rongrong TAO , Hao WANG , Jinyu XIAO , Wei SU , Shen XU , Longxing SHI
Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a threshold value Tset, calculating a time interval Ttap between adjacent zero points during a present conducting time, outputting a switch-off signal at zero points, and comparing the time interval Ttap with the preset threshold value Tset; when Ttap>Tset, he present switch-off time to be less than a switch-off time of a previous cycle, outputting a switch-on signal; when Ttap=0, controlling the present switch-off time to be greater than a switch-off time of the previous cycle, outputting a switch-on signal; and when 0
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公开(公告)号：US20230215503A1
公开(公告)日：2023-07-06
申请号：US17928333
申请日：2021-04-27
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Ming GU , Hao WANG , Shuming GUO , Youhui LI , Bin CHEN , Yongqiang HU
Abstract: A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.
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公开(公告)号：US20230146299A1
公开(公告)日：2023-05-11
申请号：US17912760
申请日：2021-07-02
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Jingchuan ZHAO , Nailong HE , Sen ZHANG , Zhili ZHANG , Hao WANG
IPC: H01L29/06 , H01L29/10 , H01L29/78 , H01L21/265 , H01L21/266 , H01L29/66
CPC classification number: H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/7816 , H01L21/26513 , H01L21/266 , H01L29/66681
Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate (101) having a second conductivity type; a drift region (102) that has a first conductivity type and is disposed on the substrate (101), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (102), each layer of the doped structure comprising at least one doped bar (105) extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars (106) disposed in the drift region (102) so as to extend downward through the doped bar (105) of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars (106) and ions doped in the doped bar have opposite conductivity types.
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公开(公告)号：US20210240898A1
公开(公告)日：2021-08-05
申请号：US17053550
申请日：2019-08-15
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Nan ZHANG , Jing ZHOU , Hao WANG , Zhan GAO , Maoqian ZHU , Cheng ZHOU , Zhijin LI , Lin WU , Shuming GUO , Yong HUANG
IPC: G06F30/367 , G06F30/392
Abstract: The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rb connected in parallel, input ends of adjacent resistors Rb are connected by means of a resistor Ra, output ends of adjacent resistors Rb are connected by means of a resistor Rc, R a = 1 N R 0 , R c = 1 N R 1 , and Rb=RDEV*N+RS+RD, wherein R0 and R1 are respectively resistances of a source metal strip and a drain metal strip, Rs is a metal resistor of a first intermediate layer connecting one source region to the source metal strip, RD is a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and RDEV is the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.
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公开(公告)号：US20200336076A1
公开(公告)日：2020-10-22
申请号：US16959116
申请日：2018-12-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. , SOUTHEAST UNIVERSITY
Inventor： Qinsong QIAN , Shengyou XU , Feng LIN , Hao WANG , Wei SU , Qi LIU , Longxing SHI
IPC: H02M3/335
Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.
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