公开(公告)号：US10347730B2

公开(公告)日：2019-07-09

申请号：US16064550

申请日：2017-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033

Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).

公开(公告)号：US11532726B2

公开(公告)日：2022-12-20

申请号：US17121360

申请日：2020-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

公开(公告)号：US10854743B2

公开(公告)日：2020-12-01

申请号：US16329663

申请日：2017-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/78 ,  H01L29/66

Abstract: A VDMOS device and a manufacturing method therefor. The manufacturing method comprises: forming a groove in a semiconductor substrate, the groove comprising a first groove area, a second groove area, a third groove area, a fourth groove area and a fifth groove area; successively forming a first insulation layer, a first polycrystalline silicon layer and a second insulation layer on the semiconductor substrate; removing some of the second insulation layer until the first polycrystalline silicon layer is exposed; removing some of the first polycrystalline silicon layer, the remaining first polycrystalline silicon layer forming a first electrode; forming a third insulation layer on the semiconductor substrate, removing some of the third insulation layer, the second insulation layer and the first insulation layer, so that the top of the first polycrystalline silicon layer is higher than the top of the first insulation layer and the second insulation layer; and successively forming a gate oxide layer and a second polycrystalline silicon layer on the semiconductor substrate, and removing some of the second polycrystalline silicon layer, exposing the gate oxide layer located on the surface of the semiconductor substrate and the top of the second insulation layer, the remaining second polycrystalline silicon layer forming a second electrode.

公开(公告)号：US10475893B2

公开(公告)日：2019-11-12

申请号：US16064522

申请日：2017-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A trench gate lead-out structure comprises a substrate (10), a trench formed in the surface of the substrate (10) and a first dielectric layer (22) on the substrate (10), and also comprises a polysilicon gate (31) at the inner surface of the trench. The trench is partially filled by the polysilicon gate (31), so that a recess exists in the trench above the polysilicon gate (31). A second dielectric layer (41) is filled in the recess. The trench gate lead-out structure also comprises a metal plug (50). The metal plug (50) downwards penetrates through the first dielectric layer (22) and then is inserted between the second dielectric layer (41) and the polysilicon gate (31), and accordingly is connected to the polysilicon gate (31).

公开(公告)号：US10373945B2

公开(公告)日：2019-08-06

申请号：US15764394

申请日：2016-08-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/16 ,  H01L29/866 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.