公开(公告)号：US09356137B2

公开(公告)日：2016-05-31

申请号：US14130483

申请日：2013-05-07

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Shu Zhang ,  Yanqiang He ,  TseHuang Lo ,  HsiaoChia Wu

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/482

CPC classification number: H01L29/7816 ,  H01L23/4824 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L29/7835 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Abstract translation: 公开了功率MOS器件结构的各种实施例。 一方面，功率MOS器件结构包括多个LDMOS和多个接合焊盘。 LDMOS的基本单元并联并电耦合到焊盘，以耦合到LDMOS的每个基本单元的栅极端子，源极端子，漏极端子和衬底。 LDMOS的基本单元设置在焊盘下方。 接合焊盘包括厚度为3.5μm至4.5μm，宽度为1.5μm至2.5μm的单层金属。 本公开的功率MOS器件的焊盘下方的区域用于增加LDMOS的基本单元的数量，从而有效地降低导通电阻。