公开(公告)号：US11901319B2

公开(公告)日：2024-02-13

申请号：US17233967

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui-Min Huang ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L21/481 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/07 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L21/568 ,  H01L23/49827 ,  H01L2224/0239 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/18162 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/27

摘要： A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

公开(公告)号：US09786616B2

公开(公告)日：2017-10-10

申请号：US15231469

申请日：2016-08-08

申请人： SEIKO EPSON CORPORATION

发明人： Kazunobu Kuwazawa ,  Hiroaki Nitta ,  Takehiro Endo ,  Mitsuo Sekisawa

IPC分类号： H01L23/488 ,  H01L23/00

CPC分类号： H01L24/04 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L24/43 ,  H01L24/47 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 μm or more, the thickness of the second insulation layer is less than or equal to ⅖ of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.

公开(公告)号：US20140084491A1

公开(公告)日：2014-03-27

申请号：US13922332

申请日：2013-06-20

申请人： Fujitsu Limited

发明人： Tetsuya TAKAHASHI ,  Yasuo MORIYA ,  Kimio NAKAMURA

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/07 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75314 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83209 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92242 ,  H01L2924/014 ,  H01L2924/0665

摘要： A method for manufacturing an electronic device, the method includes: applying an adhesive film on a package board; placing an electronic component on the package board with a bump therebetween; applying a first load to the electronic component while heating the electronic component to a first temperature higher than a reaction start temperature of the adhesive film and lower than a melting point of the bump; reducing the first load to a second load lower than the first load while maintaining the first temperature; and heating the electronic component to a second temperature higher than or equal to the melting point of the bump while maintaining the second load.

摘要翻译： 一种电子设备的制造方法，其特征在于，包括：在封装板上涂布粘合膜; 将电子部件放置在封装板上，其间具有凸块; 在将电子部件加热至高于粘合膜的反应开始温度的第一温度并低于凸点的熔点的同时向电子部件施加第一负载; 在保持第一温度的同时将第一负载减小到低于第一负载的第二负载; 并且在保持第二负载的同时将电子部件加热到高于或等于凸点的熔点的第二温度。

公开(公告)号：US20190189304A1

公开(公告)日：2019-06-20

申请号：US16326073

申请日：2018-07-02

申请人： LG CHEM, LTD.

发明人： Woo Jae JEONG ,  You Jin KYUNG ,  Byung Ju CHOI ,  Bo Yun CHOI ,  Kwang Joo LEE ,  Min Su JEONG

IPC分类号： H01B3/32 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

CPC分类号： H01B3/32 ,  H01B3/30 ,  H01L23/31 ,  H01L23/532 ,  H01L23/5329 ,  H01L24/07 ,  H01L2224/04105 ,  H01L2224/96

摘要： The present invention relates to a method for manufacturing an insulating layer which can minimize the degree of warpage caused by polymer shrinkage at the time of curing and secure the stability of a semiconductor chip located therein, and a method for manufacturing a semiconductor package using an insulating layer obtained from the manufacturing method of the insulating layer.

公开(公告)号：US20170338193A1

公开(公告)日：2017-11-23

申请号：US15520872

申请日：2015-10-14

申请人： DANFOSS SILICON POWER GMBH

发明人： Josef Lutz ,  Ronald Eisele ,  Jacek Rudzki ,  Martin Becker ,  Mathias Kock ,  Frank Osterwald

IPC分类号： H01L23/62 ,  H01L23/00

CPC分类号： H01L23/62 ,  H01L24/04 ,  H01L24/07 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48491 ,  H01L2224/85423 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/00015 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05599

摘要： A description is given of a power semiconductor module 10 which can be transferred from a normal operating mode to an explosion-free robust short-circuit failure mode. Said power semiconductor module 10 comprises a power semiconductor 1 having metallizations 3 which form potential areas and are separated by insulations and passivations on the top side 2 of said power semiconductor. Furthermore, an electrically conductive connecting layer is provided, on which at least one metal shaped body 4 which has a low lateral electrical resistance and is significantly thicker than the connecting layer is arranged, said at least one metal shaped body being applied by sintering of the connecting layer such that said metal shaped body is cohesively connected to the respective potential area. The metal shaped body 4 is embodied and designed with means for laterally homogenizing a current flowing through it in such a way that a lateral current flow component 5 is maintained until this module switches off in order to avoid an explosion, wherein the metal shaped body 4 has connections 6 having high-current capability. A transition from the operating mode to the robust failure mode then takes place in an explosion-free manner by virtue of the fact that the connections 6 are contact-connected and dimensioned in such a way that in the case of overload currents of greater than a multiple of the rated current of the power semiconductor 1, the operating mode changes to the short-circuit failure mode with connections 6 remaining on the metal shaped body 4 in an explosion-free manner without the formation of arcs.

公开(公告)号：US09717148B2

公开(公告)日：2017-07-25

申请号：US14859026

申请日：2015-09-18

申请人： Delaware Capital Formation, Inc.

发明人： Mark Hahn

IPC分类号： H05K3/10 ,  H05K1/18 ,  B23K9/167 ,  B23K9/09 ,  H01L23/00 ,  B23K26/21 ,  B23K26/0622

CPC分类号： H05K3/103 ,  B23K9/0043 ,  B23K9/091 ,  B23K9/092 ,  B23K9/167 ,  B23K9/23 ,  B23K26/0622 ,  B23K26/21 ,  B23K26/22 ,  B23K26/32 ,  B23K2101/38 ,  B23K2103/00 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L24/42 ,  H01L24/44 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02163 ,  H01L2224/02185 ,  H01L2224/04042 ,  H01L2224/45147 ,  H01L2224/45639 ,  H01L2224/48476 ,  H01L2224/80007 ,  H01L2224/80009 ,  H01L2224/8019 ,  H01L2224/8034 ,  H01L2924/00014 ,  H05K1/18 ,  H05K3/328 ,  H05K2201/10242 ,  H05K2201/10265 ,  H05K2201/10287 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

公开(公告)号：US09681545B2

公开(公告)日：2017-06-13

申请号：US15187371

申请日：2016-06-20

申请人： INNOLUX CORPORATION

发明人： Chia-Cheng Liu ,  Chia-Hsiung Chang ,  An-Chang Wang ,  Chao-Hsiang Wang ,  Yang-Chen Chen

IPC分类号： H05K1/11 ,  H05K1/09 ,  H01L23/00 ,  H05K3/32 ,  G02F1/1345 ,  H01L23/492

CPC分类号： H05K1/111 ,  G02F1/1345 ,  G02F1/13458 ,  H01L23/4922 ,  H01L24/06 ,  H01L24/07 ,  H01L24/09 ,  H01L24/26 ,  H01L24/31 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2225/1041 ,  H01L2924/13069 ,  H01L2924/365 ,  H05K1/092 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/10136

摘要： A substrate structure includes a first substrate, a plurality of first bonding pads, a second substrate and a connecting layer. The first substrate has an element configuration area and a peripheral area. The peripheral area is located around the element configuration area. The first bonding pads are configured spacing at the peripheral area, and a gap is provided between two adjacent first bonding pads. The first bonding pads are located between the first substrate and the second substrate. The connecting layer is located between the first bonding pads and the second substrate. The part of the connecting layer close to the element configuration area is configured with a plurality of first arc edges.

公开(公告)号：US09153549B2

公开(公告)日：2015-10-06

申请号：US14005941

申请日：2013-02-12

申请人： Noda Screen Co., Ltd.

发明人： Seisei Oyamada ,  Masamitsu Yoshizawa ,  Hirotaka Ogawa

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L23/60 ,  H01L23/64 ,  H01L25/065 ,  H05K1/14 ,  H05K3/36

CPC分类号： H01L24/07 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/60 ,  H01L23/64 ,  H01L24/06 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/15321 ,  H01L2924/15788 ,  H01L2924/171 ,  H01L2924/351 ,  H05K1/141 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/2036 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

摘要翻译： 半导体器件包括半导体芯片，插入器，表面电路图案和柱阵列。 表面电路图案形成在插入件的一个表面上，并且包括连接到半导体芯片的外部连接焊盘，接合焊盘和连接到芯片侧焊盘的端部的连接线的芯片侧焊盘，以及连接到芯片侧焊盘的另一端 垫 互连线从芯片侧焊盘延伸到插入器的外边缘。 柱阵列包括导电路径和将导电路径彼此绝缘的绝缘树脂。 柱阵列被布置成使得导电路径在与插入器的表面相交的方向上延伸。 导电路径各自具有连接到接合焊盘的端部，并且另一端连接到印刷线路板。

公开(公告)号：US08906781B2

公开(公告)日：2014-12-09

申请号：US14079075

申请日：2013-11-13

申请人： Siliconfile Technologies Inc.

发明人： In Gyun Jeon

IPC分类号： H01L21/46 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L27/146

CPC分类号： H01L25/50 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/06051 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention relates to a method for electrically connecting wafers, which physically bonds two wafers through an oxide-to-oxide bonding method and then electrically connects the two wafers through a butting contact structure. The wafers are physically bonded to each other through a relatively simple method, and then electrically connected to through TSVs or butting contact holes. Therefore, since the fabrication process may be simplified, a process error may be reduced, and the product yield may be improved.

摘要翻译： 本发明涉及一种用于电连接晶片的方法，其通过氧化物 - 氧化物接合方法物理地结合两个晶片，然后通过对接接触结构电连接两个晶片。 晶片通过相对简单的方法物理地彼此结合，然后通过TSV或对接接触孔电连接。 因此，由于可以简化制造工艺，可以减少加工误差，可以提高产品成品率。

公开(公告)号：US11749605B2

公开(公告)日：2023-09-05

申请号：US17116488

申请日：2020-12-09

申请人： International Business Machines Corporation

发明人： Jae-Woong Nah ,  Eric Peter Lewandowski ,  Adinath Shantinath Narasgond

IPC分类号： H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  G06N10/00 ,  H01L29/43 ,  H01L21/28

CPC分类号： H01L23/53285 ,  H01L21/76891 ,  H01L24/03 ,  H01L24/07 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/15 ,  H01L24/16 ,  G06N10/00 ,  H01L21/28026 ,  H01L29/437

摘要： Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.