公开(公告)号：US11256837B1

公开(公告)日：2022-02-22

申请号：US16946666

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Marc Heyberger ,  Manish Garg ,  Akash Khandelwal ,  Chunlong Pan ,  Ruchir Agarwal ,  Anurag Saran ,  Lalit Bharat ,  Namrata M Sadhankar ,  Manish Bhatia ,  Renuka Deshpande

IPC: G06F30/33 ,  G06F30/327 ,  G06F119/06 ,  G06F119/12

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.

公开(公告)号：US10460059B1

公开(公告)日：2019-10-29

申请号：US14747872

申请日：2015-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Akash Khandelwal ,  Pawan Kulshreshtha ,  Rajarshi Mukherjee ,  Chih-kuo Yu

IPC: G06F17/50 ,  G01R31/317

Abstract: A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.