公开(公告)号：US11494540B1

公开(公告)日：2022-11-08

申请号：US17214716

申请日：2021-03-26

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Alwin Gupta ,  Marc Heyberger ,  Manish Bhatia ,  Manish Garg

IPC: G06F30/367 ,  G06F30/373 ,  G06F30/3312 ,  G06F30/398 ,  G06F30/3315 ,  G06F119/06 ,  G06F119/12

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.

公开(公告)号：US11256837B1

公开(公告)日：2022-02-22

申请号：US16946666

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Marc Heyberger ,  Manish Garg ,  Akash Khandelwal ,  Chunlong Pan ,  Ruchir Agarwal ,  Anurag Saran ,  Lalit Bharat ,  Namrata M Sadhankar ,  Manish Bhatia ,  Renuka Deshpande

IPC: G06F30/33 ,  G06F30/327 ,  G06F119/06 ,  G06F119/12

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.

公开(公告)号：US08875082B1

公开(公告)日：2014-10-28

申请号：US13729665

申请日：2012-12-28

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Manish Garg

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5031

Abstract: A system and method for expeditious operational timing signoff of a circuit design through a timing analysis and subsequent corrective or remedial optimization is performed with the goal of correlating timing between the physical implementation corrective optimizer module and the timing analysis module to reduce iterations therebetween. A physical optimizer in the correction module is imparted with knowledge of the physical implementation of the design to allow for legal, non-conflicting placement of corrective buffers or resizing of gates in accordance with the physical implementation data of the circuit design.

Abstract translation: 通过定时分析和随后的校正或补救优化来执行电路设计的快速操作定时签发的系统和方法，目的是使物理实现校正优化器模块和时序分析模块之间的时序相关联，以减少它们之间的迭代。 校正模块中的物理优化器被赋予了设计的物理实现的知识，以便根据电路设计的物理实现数据允许校正缓冲器的合法，非冲突的放置或门的大小调整。