公开(公告)号：US11494540B1

公开(公告)日：2022-11-08

申请号：US17214716

申请日：2021-03-26

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Alwin Gupta ,  Marc Heyberger ,  Manish Bhatia ,  Manish Garg

IPC: G06F30/367 ,  G06F30/373 ,  G06F30/3312 ,  G06F30/398 ,  G06F30/3315 ,  G06F119/06 ,  G06F119/12

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.

公开(公告)号：US11256837B1

公开(公告)日：2022-02-22

申请号：US16946666

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Marc Heyberger ,  Manish Garg ,  Akash Khandelwal ,  Chunlong Pan ,  Ruchir Agarwal ,  Anurag Saran ,  Lalit Bharat ,  Namrata M Sadhankar ,  Manish Bhatia ,  Renuka Deshpande

IPC: G06F30/33 ,  G06F30/327 ,  G06F119/06 ,  G06F119/12

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.