公开(公告)号：US10586011B1

公开(公告)日：2020-03-10

申请号：US15928627

申请日：2018-03-22

Applicant: Cadence Design Systems, Inc.

Inventor： Dennis Nagle ,  Amit Kumar Sharma ,  Delong Cai ,  Xuegang Zeng ,  Hui Qi

IPC: G06F17/50

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

公开(公告)号：US09619605B1

公开(公告)日：2017-04-11

申请号：US13949549

申请日：2013-07-24

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Vikas Kohli ,  Amit Kumar Sharma

IPC: G06F15/04 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/06 ,  G06F2217/74

Abstract: A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.

公开(公告)号：US09122384B1

公开(公告)日：2015-09-01

申请号：US13949578

申请日：2013-07-24

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Vikas Kohli ,  Amit Kumar Sharma

IPC: G09G5/02 ,  G09G5/36 ,  G06T11/00 ,  G06T19/00 ,  G06F3/0481 ,  G06F3/14 ,  G06F3/0484

CPC classification number: G09G5/02 ,  G06F3/0481 ,  G06F17/5068 ,  G06F2217/74 ,  G06T11/001

Abstract: A method and system are provided for maintaining dynamic visual cues/graphic indicia for associated circuitry of a schematic object. The dynamic visual cues or graphic indicia indicate a number of states of the parent circuit object and its associated circuitry. The visibility, placement status, and other attributes of the parent or associated circuitry may be quickly discerned by inspection of the visual indicia. Navigation, including manipulations of one or both of the parent and associated circuitry are available through actuation of the visual cue or a selectable button proximately disposed thereto.

Abstract translation: 提供了一种方法和系统，用于维持示意图对象的相关电路的动态视觉提示/图形标记。 动态视觉提示或图形标记表示父电路对象及其相关电路的多个状态。 母体或相关电路的可视性，放置状态和其他属性可以通过视觉标记的检查快速识别。 导航，包括母机和相关电路中的一个或两者的操作可通过致动视觉提示或近似设置于其上的可选按钮来获得。