公开(公告)号：US10606974B1

公开(公告)日：2020-03-31

申请号：US15911421

申请日：2018-03-05

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Amiya Acharya ,  Vikas Kohli

IPC: G06F17/50 ,  G06F13/42 ,  H03F3/213 ,  H03F3/195

Abstract: In an electronic circuit design system, dynamic visual guidance for relative placement of mutually paired electronic components, such as a bypass capacitance portion and a power pin in a power domain, is provided. A first, selected component is adaptively paired with one of a plurality of second components eligible for pairing with the first component, according to predetermined pairing criteria such as proximity criteria. A mutual placement zone between the paired components is generated to define a locus of valid placement locations of the paired first and second components one with respect to the other according to predetermined placement criteria therefor. Visual indicia to represent the mutual placement zone is generated, thereby providing visual guidance to reposition the first component.

公开(公告)号：US10285276B1

公开(公告)日：2019-05-07

申请号：US15275230

申请日：2016-09-23

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Kukal ,  Arnold Ginetti ,  Steven R. Durrill ,  Abhay Agarwal ,  Vikas Kohli ,  Tyler Lockman

IPC: G06F11/22 ,  G06F17/50 ,  H05K3/00

Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

公开(公告)号：US11593437B1

公开(公告)日：2023-02-28

申请号：US16691800

申请日：2019-11-22

Applicant: Cadence Design Systems, Inc.

Inventor： Daniel Konrad Fernsebner ,  Vikas Kakkar ,  Vikas Kohli ,  Mark Joseph Hepburn

IPC: G06F16/9038 ,  G06F16/903 ,  G06F30/31 ,  G06F111/02 ,  G06F115/08 ,  G06F111/04

Abstract: The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.

公开(公告)号：US09280621B1

公开(公告)日：2016-03-08

申请号：US14503407

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Vikas Kohli ,  Taranjit Singh Kukal

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are techniques to analyze multi-fabric designs. These techniques generate a cross-fabric analysis model by at least identifying first design data in a first design fabric of a multi-fabric electronic design using a first session of a first electronic design automation (EDA) tool, update the cross-fabric simulation model by at least identifying second design data in a second design fabric using a second session of a second EDA tool, and determine analysis results for the multi-fabric electronic design using at least the cross-fabric simulation model. Analysis results may be determined using parasitic, electrical, or performance information. Various EDA tools access their respective native design data in their respective domains or design fabrics and have no access to or visibility of non-native design data while these techniques automatically cross the boundaries between multiple design fabrics to accomplish the tasks of analyzing multi-fabric electronic designs or displaying analysis results therefor.

Abstract translation: 公开了分析多织物设计的技术。 这些技术通过使用第一电子设计自动化（EDA）工具的第一会话至少识别多结构电子设计的第一设计结构中的第一设计数据来生成交叉结构分析模型，更新交织架模拟模型 通过使用第二EDA工具的第二会话至少识别第二设计结构中的第二设计数据，并使用至少交叉结构仿真模型确定多结构电子设计的分析结果。 可以使用寄生，电气或性能信息来确定分析结果。 各种EDA工具在其各自的领域或设计结构中访问其各自的本机设计数据，并且无法访问或了解非本地设计数据，而这些技术自动跨越多个设计结构之间的边界，从而完成分析多结构电子 设计或展示分析结果。

公开(公告)号：US09223915B1

公开(公告)日：2015-12-29

申请号：US14503406

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Vikas Kohli ,  Taranjit Singh Kukal

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are various techniques that check, verify, or test multi-fabric designs by receiving a request for checking correctness of a multi-fabric design across at least a first design fabric and a second design fabric. A request for action is transmitted from a first EDA tool session to a second EDA tool session. Connectivity information of second design data in the second design fabric is identified by the second EDA tool session in response to the request for action from the first EDA tool session. These various techniques then check the correctness of the multi-fabric design in the first design fabric by using at least the connectivity information of the second design data. A symbolic representation may be used to represent design data in an EDA tool session to which the design data are not native.

Abstract translation: 公开了通过接收至少第一设计结构和第二设计结构来检查多织物设计的正确性的请求来检查，验证或测试多织物设计的各种技术。 将动作请求从第一EDA工具会话发送到第二EDA工具会话。 响应于来自第一EDA工具会话的动作请求，第二设计结构中的第二设计数据的连接信息由第二EDA工具会话识别。 然后，这些各种技术至少使用第二设计数据的连接性信息来检查第一设计结构中的多结构设计的正确性。 符号表示可用于表示设计数据不是本机的EDA工具会话中的设计数据。

公开(公告)号：US09202006B1

公开(公告)日：2015-12-01

申请号：US14550038

申请日：2014-11-21

Applicant: Cadence Design Systems, Inc.

Inventor： Utpal Bhattacharya ,  Vikas Kohli

IPC: G06F17/50 ,  G06F3/0484 ,  G06F3/0482

CPC classification number: G06F17/5081 ,  G06F17/5045

Abstract: The present disclosure relates to a computer-implemented method for visualization in an electronic design. The method may include providing an electronic design and receiving a selection of at least one pin associated with the electronic design at a first graphical user interface. The method may further include generating a stub for each of the selected pins at the first graphical user interface. The method may also include providing a second graphical user interface configured to allow for the assignment of a signal name to each stub. The method may include extending the stub for each of the selected pins to reach a target destination associated with the electronic design. The method may also include displaying the signal name for each stub on at least one of the first graphical user interface and the second graphical user interface.

Abstract translation: 本公开涉及一种用于在电子设计中可视化的计算机实现的方法。 该方法可以包括提供电子设计并且在第一图形用户界面处接收与电子设计相关联的至少一个引脚的选择。 该方法还可以包括在第一图形用户界面处为每个所选择的引脚生成短截线。 该方法还可以包括提供配置为允许向每个存根分配信号名称的第二图形用户界面。 该方法可以包括为每个所选择的引脚延伸短截线以到达与电子设计相关联的目标目的地。 该方法还可以包括在第一图形用户界面和第二图形用户界面中的至少一个上显示每个存根的信号名称。

公开(公告)号：US09361415B1

公开(公告)日：2016-06-07

申请号：US14503403

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Taranjit Singh Kukal ,  Vikas Kohli

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

Abstract: Various embodiments implement multi-fabric designs by using respective EDA tools associated with multiple design fabrics to access their respective native design data. Each EDA tool has access to and processes or manipulates its corresponding native design data; and no EDA tools have the visibility of the entire multi-fabric electronic design. Requests for actions are automatically transmitted among these EDA tools to instantiate desired EDA tools and to descend or ascend the multi-fabric design structure so that native design data in a particular design fabric are processed by the corresponding EDA tool(s) within the context of the other design fabrics. These techniques enable designers to implement, check, verify, simulate, analyze, probe, and netlist the entire electronic design across multiple design fabric.

Abstract translation: 各种实施例通过使用与多个设计结构相关联的相应EDA工具来访问其各自的本机设计数据来实现多结构设计。 每个EDA工具都可以访问和处理或操纵其对应的本地设计数据; 并且没有EDA工具可以看到整个多结构的电子设计。 在这些EDA工具之间自动传送动作请求，以实例化所需的EDA工具，并下降或上升多结构设计结构，使特定设计结构中的本机设计数据由相应的EDA工具在上下文中进行处理 其他设计面料。 这些技术使设计人员能够跨多个设计架构实施，检查，验证，模拟，分析，探测和整理电子设计。

公开(公告)号：US09348960B1

公开(公告)日：2016-05-24

申请号：US14503404

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Taranjit Singh Kukal ,  Vikas Kohli

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/04 ,  G06F2217/08 ,  G06F2217/38 ,  G06F2217/40 ,  G06F2217/74

Abstract: Described are methods and systems for netlisting or probing multi-fabric designs that identify a request for process at least a portion of a multi-fabric electronic design and determine a first partial listing of one or more first circuit components in response to the request by at least identifying first design data in a first design fabric of the one or more first circuit components using a first session of a first electronic design automation (EDA) tool. The methods and systems further automatically transmit a request for action related to the one or more first circuit components from the first session to a second session of a second EDA tool and determine a second partial listing of one or more second circuit components by at least identifying second design data in a second design fabric of the one or more second circuit components using the second session.

Abstract translation: 描述了用于网络列表或探测多结构设计的方法和系统，其识别处理多结构电子设计的至少一部分的请求，并且响应于在第一电路组件的请求确定一个或多个第一电路组件的第一部分列表 使用第一电子设计自动化（EDA）工具的第一会话来最小化所述一个或多个第一电路组件的第一设计结构中的第一设计数据。 所述方法和系统进一步自动地将与所述一个或多个第一电路组件相关的动作请求从第一会话发送到第二EDA工具的第二会话，并且通过至少识别一个或多个第二电路组件来确定第二部分列表 使用第二会话的一个或多个第二电路组件的第二设计结构中的第二设计数据。

公开(公告)号：US10289788B1

公开(公告)日：2019-05-14

申请号：US14954033

申请日：2015-11-30

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Matthew Timothy Bromley ,  Vikas Kohli ,  Sagar Kumar

IPC: G06F17/50 ,  G06F16/22 ,  G06F16/28

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.

公开(公告)号：US09619605B1

公开(公告)日：2017-04-11

申请号：US13949549

申请日：2013-07-24

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Vikas Kohli ,  Amit Kumar Sharma

IPC: G06F15/04 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/06 ,  G06F2217/74

Abstract: A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.