公开(公告)号：US11507720B1

公开(公告)日：2022-11-22

申请号：US17345857

申请日：2021-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： Matheus Nogueira Fonseca ,  Thamara Karen Cunha Andrade ,  Lars Lundgren ,  Breno Guimaraes

IPC: G06F30/30 ,  G01R31/317 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/31 ,  G06F119/12

Abstract: This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

公开(公告)号：US20240311538A1

公开(公告)日：2024-09-19

申请号：US18121143

申请日：2023-03-14

Applicant: Cadence Design Systems, Inc.

Inventor： Matheus Nogueira Fonseca ,  Lars Lundgren ,  Gabriel Guedes de Azevedo Barbosa ,  Paula Selegato Mathias ,  Luis Humberto Rezende Barbosa ,  Bárbara Leite Almeida ,  Thamara Karen Cunha Andrade ,  Gustavo Augusto Silva Junqueira ,  João Paulo Magalhães de Melo dos Santos

IPC: G06F30/327 ,  G06F11/36 ,  G06F30/331

CPC classification number: G06F30/327 ,  G06F11/3652 ,  G06F30/331 ,  G06F2119/12

Abstract: Embodiments include herein are directed towards a system and method for glitch debugging in an electronic design. Embodiments may include receiving, using a processor, the electronic design and performing a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design. If a glitch is identified, embodiments may further include causing a generation of a graphical glitch debugger display. Embodiments may include receiving an edit to the electronic design and re-performing the formal glitch analysis of the electronic design to determine whether a glitch is present.

公开(公告)号：US10936776B1

公开(公告)日：2021-03-02

申请号：US16834777

申请日：2020-03-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Thamara Karen Cunha Andrade ,  Ronalu Augusta Nunes Barcelos ,  Gabriel Peres Nobre ,  Igor Tiradentes Murta ,  Vitor Machado Guilherme Barros ,  Rafael Sales Medina Ferreira ,  Marcos Augusto de Goes

IPC: G06F30/33 ,  G06F30/333 ,  G06F9/30 ,  G06F8/71 ,  G06F30/20

Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.

公开(公告)号：US10796051B1

公开(公告)日：2020-10-06

申请号：US16399536

申请日：2019-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Abner Luis Panho Marciano ,  Matheus Fonseca ,  Thamara Karen Cunha Andrade ,  Raquel Lara dos Santos Pereira ,  Fabiano Cruz Peixoto ,  Rodolfo Santos Teixeira ,  Rafael Gontijo Hamdan ,  Bruno Andrade Pereira

IPC: G06F30/00 ,  G06F30/3323 ,  G06F30/3312 ,  G06F111/04 ,  G06F111/20

Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.