公开(公告)号：US10769008B1

公开(公告)日：2020-09-08

申请号：US15370565

申请日：2016-12-06

Applicant: Cadence Design Systems, Inc.

Inventor： Alberto Manuel Arias Drake ,  Andrea Iabrudi Tavares ,  Artur Melo Mota Costa ,  Fabiano Cruz Peixoto ,  Laiz Lipiainen Santos ,  Lucas Ferreira de Melo Diniz ,  Nathália Peixoto Reis ,  Patricia Sette Câmara Haizer ,  Regina Mara Amaral Fonseca ,  Tamires Vargas Capanema Franco Santos

IPC: G06F11/00 ,  G06F11/07

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.

公开(公告)号：US10540467B1

公开(公告)日：2020-01-21

申请号：US15943819

申请日：2018-04-03

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Abner Luis Panho Marciano ,  Matheus Nogueira Fonseca ,  Ronalu Augusta Nunes Barcelos ,  Fabiano Cruz Peixoto

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

公开(公告)号：US10796051B1

公开(公告)日：2020-10-06

申请号：US16399536

申请日：2019-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Abner Luis Panho Marciano ,  Matheus Fonseca ,  Thamara Karen Cunha Andrade ,  Raquel Lara dos Santos Pereira ,  Fabiano Cruz Peixoto ,  Rodolfo Santos Teixeira ,  Rafael Gontijo Hamdan ,  Bruno Andrade Pereira

IPC: G06F30/00 ,  G06F30/3323 ,  G06F30/3312 ,  G06F111/04 ,  G06F111/20

Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.