公开(公告)号：US10521531B1

公开(公告)日：2019-12-31

申请号：US15808326

申请日：2017-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Frederico Nascimento-Yoshida ,  Matheus Nogueira Fonseca

IPC: G06F9/455 ,  G06F17/50 ,  H04W80/12

Abstract: The present disclosure relates to a method for formal verification of an electronic design. Embodiments may include receiving, using a processor, an electronic design having a plurality of clock configurations associated therewith and identifying a target clock configuration associated with the electronic design. Embodiments may also include receiving a range of clock factor values from a user, wherein each clock factor value corresponds to a frequency of the target clock configuration. Embodiments may further include selecting, via a formal engine, at least one clock factor value from the range and selecting, via the formal engine, at least one clock phase associated with the target clock configuration. Embodiments may also include performing formal verification of the electronic design, based upon, at least in part, the at least one clock factor value or the at least one clock phase.

公开(公告)号：US10783305B1

公开(公告)日：2020-09-22

申请号：US16275280

申请日：2019-02-13

Applicant: Cadence Design Systems, Inc.

Inventor： Matheus Nogueira Fonseca ,  Tulio Paschoalin Leao

IPC: G06F30/3323 ,  G06F30/30 ,  G06F119/12

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments may also include generating a property that determines whether an input and an output of the sequential element is never different and determining whether the property is true using formal verification.

公开(公告)号：US20240311538A1

公开(公告)日：2024-09-19

申请号：US18121143

申请日：2023-03-14

Applicant: Cadence Design Systems, Inc.

Inventor： Matheus Nogueira Fonseca ,  Lars Lundgren ,  Gabriel Guedes de Azevedo Barbosa ,  Paula Selegato Mathias ,  Luis Humberto Rezende Barbosa ,  Bárbara Leite Almeida ,  Thamara Karen Cunha Andrade ,  Gustavo Augusto Silva Junqueira ,  João Paulo Magalhães de Melo dos Santos

IPC: G06F30/327 ,  G06F11/36 ,  G06F30/331

CPC classification number: G06F30/327 ,  G06F11/3652 ,  G06F30/331 ,  G06F2119/12

Abstract: Embodiments include herein are directed towards a system and method for glitch debugging in an electronic design. Embodiments may include receiving, using a processor, the electronic design and performing a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design. If a glitch is identified, embodiments may further include causing a generation of a graphical glitch debugger display. Embodiments may include receiving an edit to the electronic design and re-performing the formal glitch analysis of the electronic design to determine whether a glitch is present.

公开(公告)号：US11507720B1

公开(公告)日：2022-11-22

申请号：US17345857

申请日：2021-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： Matheus Nogueira Fonseca ,  Thamara Karen Cunha Andrade ,  Lars Lundgren ,  Breno Guimaraes

IPC: G06F30/30 ,  G01R31/317 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/31 ,  G06F119/12

Abstract: This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

公开(公告)号：US10540467B1

公开(公告)日：2020-01-21

申请号：US15943819

申请日：2018-04-03

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Abner Luis Panho Marciano ,  Matheus Nogueira Fonseca ,  Ronalu Augusta Nunes Barcelos ,  Fabiano Cruz Peixoto

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.