公开(公告)号：US11580284B1

公开(公告)日：2023-02-14

申请号：US17142360

申请日：2021-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Christopher William Komar ,  Lars Lundgren

IPC: G06F30/30 ,  G06F30/33 ,  G06F30/31 ,  G06F111/04 ,  G06Q10/10

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

公开(公告)号：US11138355B1

公开(公告)日：2021-10-05

申请号：US17099301

申请日：2020-11-16

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Maayan Ziv ,  Kanwar Pal Singh ,  Nizar Hanna ,  Gasob Mazzawi

IPC: G06F30/327 ,  G06F30/394 ,  G06F30/398 ,  G06F30/333 ,  G06F30/3323 ,  G06F30/3308

Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip, the circuit design of the IC chip including a list of properties for the IC chip. The list of properties includes a list of covers for the IC chip. The formal verification engine can also execute a formal verification of the IC chip. Results of the formal verification identifies a subset of covers of the list of covers that are unreachable. The formal verification engine can further execute a root cause search for a selected cover in the subset of covers that are unreachable. The root cause search selectively adds and removes cutpoints to signals in the circuit design to identify a root cause for the selected cover being unreachable. The root cause comprises a signal in the circuit design that is upstream from the selected cover.

公开(公告)号：US10380312B1

公开(公告)日：2019-08-13

申请号：US15371449

申请日：2016-12-07

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Lars Lundgren

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying one or more assumptions associated with the electronic design that are mutually in conflict. Embodiments may further include grouping the one or more assumptions that are mutually in conflict into a conflicting group of assumptions and iteratively disabling at least one of the conflicting group of assumptions. Embodiments may include generating at least one trace pair depicting a scenario where an assumption from a disabled set holds in a first trace but is violated in a second trace. Embodiments may further include identifying at least one signal associated with the first trace and at least one signal associated with the second trace and comparing the at least one signal associated with the first trace and the at least one signal associated with the second trace.

公开(公告)号：US10540467B1

公开(公告)日：2020-01-21

申请号：US15943819

申请日：2018-04-03

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Abner Luis Panho Marciano ,  Matheus Nogueira Fonseca ,  Ronalu Augusta Nunes Barcelos ,  Fabiano Cruz Peixoto

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.