公开(公告)号：US11463094B1

公开(公告)日：2022-10-04

申请号：US17305573

申请日：2021-07-09

Applicant: Cadence Design Systems, Inc.

Inventor： Mathieu Gagnon

IPC: H03L7/087 ,  H03L7/08 ,  H04L25/03

Abstract: Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.

公开(公告)号：US11463284B1

公开(公告)日：2022-10-04

申请号：US17305572

申请日：2021-07-09

Applicant: Cadence Design Systems, Inc.

Inventor： Mathieu Gagnon

IPC: H04L25/03

Abstract: Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.

公开(公告)号：US10547475B1

公开(公告)日：2020-01-28

申请号：US16283320

申请日：2019-02-22

Applicant: Cadence Design Systems, Inc.

Inventor： Mathieu Gagnon

IPC: H04L25/03

Abstract: A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an average amplitude of the data signal samples when data symbols of a current UI have the first symbol type and data symbols of a first UI, at a first determined time distance from the current UI, have a second symbol type, and computes, as a first cursor value associated with the first UI, a first difference between the first threshold and the second threshold, multiplied by a first constant.

公开(公告)号：US11356304B1

公开(公告)日：2022-06-07

申请号：US17305576

申请日：2021-07-09

Applicant: Cadence Design Systems, Inc.

Inventor： Guillaume Fortin ,  Jean-Francois Delage ,  Louis-Francois Tanguay ,  Mathieu Gagnon

IPC: H04L25/03

Abstract: Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.)

公开(公告)号：US10225115B1

公开(公告)日：2019-03-05

申请号：US15286432

申请日：2016-10-05

Applicant: Cadence Design Systems, Inc.

Inventor： Mathieu Gagnon ,  Santiago Luis Bortman ,  Eric Harris Naviasky ,  Guillaume Fortin ,  Julien Faucher

IPC: G06F1/12 ,  H03K5/24 ,  G11C27/02 ,  H04L25/06

Abstract: A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.

公开(公告)号：US09531529B1

公开(公告)日：2016-12-27

申请号：US14970777

申请日：2015-12-16

Applicant: Cadence Design Systems, Inc.

Inventor： Mathieu Gagnon ,  Jean-Francois Delage

IPC: H04L7/04 ,  H04B1/06 ,  H04L7/033

CPC classification number: H04L7/033 ,  H03M9/00 ,  H04L7/0004 ,  H04L7/0337

Abstract: The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery (“CDR”) loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock module is required, wherein determining includes determining two transitions in a sampling triplet. If it is determined that the fast-phase lock module is required, embodiments may include providing a trigger signal to the fast-phase lock module. Embodiments may further include receiving the trigger signal at the fast-phase lock module associated with the electronic circuit and performing a fast-phase lock operation on the signal.

Abstract translation: 本公开涉及用于检测电子电路中的时钟和数据恢复回路鞍点锁定的方法和装置。 实施例可以包括在与电子电路相关联的主时钟和数据恢复（“CDR”）环路处接收信号，并使用包括在主CDR环路内的第一级CDR环路和第二级CDR环路中的至少一个来处理信号 。 实施例还可以包括确定是否需要快速锁相模块，其中确定包括确定采样三元组中的两个转变。 如果确定需要快速锁相模块，则实施例可以包括向快速锁相模块提供触发信号。 实施例还可以包括在与电子电路相关联的快速锁相模块处接收触发信号，并对该信号执行快速锁相操作。