System and method for saddle point locking detection during clock and data recovery
    6.
    发明授权
    System and method for saddle point locking detection during clock and data recovery 有权
    在时钟和数据恢复期间用于鞍点锁定检测的系统和方法

    公开(公告)号:US09531529B1

    公开(公告)日:2016-12-27

    申请号:US14970777

    申请日:2015-12-16

    CPC classification number: H04L7/033 H03M9/00 H04L7/0004 H04L7/0337

    Abstract: The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery (“CDR”) loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock module is required, wherein determining includes determining two transitions in a sampling triplet. If it is determined that the fast-phase lock module is required, embodiments may include providing a trigger signal to the fast-phase lock module. Embodiments may further include receiving the trigger signal at the fast-phase lock module associated with the electronic circuit and performing a fast-phase lock operation on the signal.

    Abstract translation: 本公开涉及用于检测电子电路中的时钟和数据恢复回路鞍点锁定的方法和装置。 实施例可以包括在与电子电路相关联的主时钟和数据恢复(“CDR”)环路处接收信号,并使用包括在主CDR环路内的第一级CDR环路和第二级CDR环路中的至少一个来处理信号 。 实施例还可以包括确定是否需要快速锁相模块,其中确定包括确定采样三元组中的两个转变。 如果确定需要快速锁相模块,则实施例可以包括向快速锁相模块提供触发信号。 实施例还可以包括在与电子电路相关联的快速锁相模块处接收触发信号,并对该信号执行快速锁相操作。

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