System, method, and computer program product for analog and mix-signal circuit placement

    公开(公告)号:US12045730B1

    公开(公告)日:2024-07-23

    申请号:US16238274

    申请日:2019-01-02

    CPC classification number: G06N3/126 G06F30/392

    Abstract: The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

    System, method, and computer program product for determining computational requirements of a printed circuit board design

    公开(公告)号:US11379646B1

    公开(公告)日:2022-07-05

    申请号:US17002976

    申请日:2020-08-26

    Abstract: The present disclosure relates to electronic circuit design, and more specifically, to determining the computational requirements of fully synthesizing a printed circuit board and/or package. Embodiments may include receiving, using a processor, one or more PCB electronic design files and determining whether the PCB electronic design files include data required for a synthesis engine. If any data is missing, the method may include inferring one or more parameters using an inference engine and providing the one or more parameters to the synthesis engine, wherein the synthesis engine includes at least one of a placement, via assignment, routing, and metal pouring processes. The method may also include collecting process data from the placement, via assignment, routing, and metal pouring processes and training a machine learning system using the process data.

    Automated Printed Circuit Board Component Clustering

    公开(公告)号:US20250053722A1

    公开(公告)日:2025-02-13

    申请号:US18448348

    申请日:2023-08-11

    Abstract: The present disclosure relates to a system and method for automated printed circuit board (PCB) component placement. Embodiments may include receiving a PCB outline, one or more constraints, and a netlist having PCB component details and applying a clustering algorithm to generate one or more clustered groups. Embodiments may further include applying a grid based local cluster placement algorithm to the one or more clustered groups. Embodiments may also include applying a global cluster placement algorithm and generating a fully optimized placed design.

    System and method for autonomous printed circuit board design using machine learning techniques

    公开(公告)号:US11599699B1

    公开(公告)日:2023-03-07

    申请号:US16785972

    申请日:2020-02-10

    Abstract: The present disclosure relates to systems and methods for floorplanning using machine learning techniques. Embodiments may include receiving an electronic design and analyzing the electronic design using a reinforcement learning agent. Embodiments may further include recommending a first action wherein the first action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the electronic design based upon, at least in part, the first action to generate an updated electronic design. Embodiments may further include analyzing the updated electronic design using the reinforcement learning agent and recommending a second action wherein the second action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the updated electronic design based upon the second action to generate a second updated electronic design.

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