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1.发明授权Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type 失效用于制造具有两种级别的多晶硅用于EEPROM类型的器件的存储器单元的工艺
公开(公告)号：US5985718A
公开(公告)日：1999-11-16
申请号：US996922
申请日：1997-12-23
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.
摘要翻译： 一种用于制造具有两级多晶硅并且被包括在EEPROM类型的存储器件中的存储单元的工艺，其中该器件形成在具有第一导电类型的半导体材料衬底上。 该方法包括以下步骤：在衬底上形成由先前形成在同一衬底上的栅极氧化物区域围绕的薄的隧道氧化物区域，在栅极氧化物区域和薄的隧道氧化物区域上沉积多晶硅层，并依次沉积 多晶硅层上的复合ONO层和附加多晶硅层。 具有窗口的电容注入掩模通过在附加多晶硅层上沉积感光材料层而形成，通过窗口以能量注入掺杂剂并且具有有效穿透多晶硅，ONO和多晶硅层的剂量 并且在薄隧道氧化物区域的横向和下方形成电连续性区域。
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2.发明授权公开(公告)号：US06432762B1
公开(公告)日：2002-08-13
申请号：US09534253
申请日：2000-03-23
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.
摘要翻译： 用于EEPROM型器件的存储单元，形成在具有第一导电类型的半导体材料衬底的一部分中。 存储单元包括具有第二导电类型的源极和漏极区域，并且在包括薄的隧道氧化物区域的栅极氧化物区域的侧面延伸。 存储单元还包括具有第二导电类型的电连续性区域，横向形成在薄隧道氧化物区域下方，并且部分地与漏极区域重叠，以及在电连通区域和源极区域之间延伸的沟道区域。 存储单元还包括具有第一导电类型并且横向形成在栅极氧化物区域下方并且结合沟道区域的注入区域。
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3.发明授权Process for the manufacturing of an electrically programmable non-volatile memory device 有权用于制造电可编程非易失性存储器件的工艺公开(公告)号：US06194270B1
公开(公告)日：2001-02-27
申请号：US09130720
申请日：1998-08-06
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/11546
摘要： Process for manufacturing an electrically programmable non-volatile memory device having electrically programmable non-volatile memory cells comprising floating-gate MOS transistors, a first kind of MOSFETs, and a second kind of MOSFETs capable of substaining gate voltages higher than that sustainable by the MOSFETs of the first kind. The process includes forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the MOSFETs of the first kind, and a third gate oxide layer for the MOSFETs of the second kind. The first gate oxide layer further comprises a tunnel oxide region. The process provides for: forming over the surface of a semiconductor material a first layer of oxide; selectively removing the first layer of oxide from regions of said surface dedicated to the MOSFETs of the first kind, but not from the regions dedicated to the floating-gate MOS transistors nor to the MOSFETs of the second kind; forming a second layer of oxide over the first layer of oxide and over said regions dedicated to the MOSFETs of the first kind; simultaneously removing the first and the second layer of oxide only from the tunnel oxide region of the floating-gate MOS transistors; and forming over the second layer of oxide and over said tunnel region oxide for the floating-gate MOS transistors a tunnel oxide layer. The third gate oxide layer and said first gate oxide layer, except in the tunnel oxide region, are formed by the superposition of the first layer of oxide, while the second layer of oxide and the tunnel oxide layer, said second gate oxide layer being formed by the superposition of the second layer of oxide and the tunnel oxide layer.
摘要翻译： 用于制造具有电可编程非易失性存储单元的电可编程非易失性存储器件的方法，所述非易失性存储器单元包括浮置栅极MOS晶体管，第一种MOSFET和能够将栅极电压高于由MOSFET可持续的栅极电压的第二种MOSFET 的第一种。 该工艺包括形成用于浮置栅极MOS晶体管的第一栅极氧化物层，用于第一种MOSFET的第二栅极氧化物层和用于第二种MOSFET的第三栅极氧化物层。 第一栅极氧化物层还包括隧道氧化物区域。 该方法提供：在半导体材料的表面上形成第一层氧化物; 从专用于第一种MOSFET的所述表面的区域中，而不是从专用于浮栅MOS晶体管的区域到第二类MOSFET的区域中选择性地去除第一层氧化物; 在第一层氧化物上形成第二层氧化物，并在专用于第一类MOSFET的所述区域上形成第二层氧化物; 同时从浮栅MOS晶体管的隧道氧化物区域去除第一和第二层氧化物; 并在所述第二层氧化物上形成所述隧道区氧化物，以使所述浮栅MOS晶体管成为隧道氧化物层。 除隧道氧化物区域外的第三栅极氧化物层和第一栅极氧化物层通过第一层氧化物的叠加形成，而第二层氧化物和隧道氧化物层形成，所述第二栅极氧化物层形成 通过第二层氧化物和隧道氧化物层的叠加。
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4.发明授权Process for the manufacturing of an electrically programmable non-volatile memory device 有权用于制造电可编程非易失性存储器件的工艺公开(公告)号：US06437395B2
公开(公告)日：2002-08-20
申请号：US09776105
申请日：2001-02-01
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/11546
摘要： A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.
摘要翻译： 一种用于制造具有浮栅MOS晶体管的可编程非易失性存储器件的工艺，以及第一和第二MOSFET，通过形成用于浮置栅极的第一栅极氧化层，能够维持比第一MOSFET高的栅极电压的第二MOSFET MOS晶体管，用于第一MOSFET的第二栅极氧化层，以及用于第二MOSFET的第三栅极氧化物层。 该方法包括：在衬底上形成第一氧化物层; 选择性地从第一MOSFET上的表面区域去除第一氧化物层，而不是从浮置栅极MOS晶体管或第二MOSFET上的表面区域去除第一氧化物层; 在所述第一氧化物层和所述第一MOSFET上的区域上形成第二氧化物层; 从所述浮栅MOS晶体管的隧道氧化物区域去除所述第一和第二氧化物层; 以及在所述第二氧化物层和隧道区氧化物层上形成隧道氧化物层。
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5.发明授权公开(公告)号：US06320219B1
公开(公告)日：2001-11-20
申请号：US09576168
申请日：2000-05-22
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.
摘要翻译： 形成在具有第一导电类型的半导体材料基板上的EEPROM型存储单元包括具有第二导电类型的漏极区域，并且在包括薄隧道氧化物区域的栅极氧化物区域的一侧延伸。 存储单元还包括具有第二导电类型的电连续性区域，横向形成在薄隧道氧化物区域下方，并且部分地与漏极区域重叠。 通过以预定的倾斜角度的注入产生电连续性的区域。
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6.发明授权Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method 有权具有通过注入调整其阈值的EEPROM类型的存储单元以及制造方法公开(公告)号：US06329254B1
公开(公告)日：2001-12-11
申请号：US09431301
申请日：1999-10-29
IPC分类号： H01L21326
CPC分类号： H01L27/11521 , H01L21/2652 , H01L27/115 , H01L27/11524 , H01L29/66825
摘要： A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.
摘要翻译： 一种工艺形成了结合有至少一个电路晶体管和EEPROM型的至少一个非易失性存储单元的结构，其中两个自对准多晶硅层具有存储晶体管和相关选择晶体管，该半导体材料包括场氧化物区域 边界活跃区域。 该方法包括以下步骤：在有源区域中，形成栅极氧化物层并限定栅极氧化物层中包括的隧道氧化物区域，沉积并部分地限定形成多晶硅互连层的第一多晶硅层，并至少除去多晶硅绝缘层 在电路晶体管处沉积第二多晶硅层选择性地蚀刻掉电池处的第二多晶硅层，以及在电路晶体管处的第一和第二多晶硅层，并且选择性地蚀刻离开电池的多晶硅间介电层和第一多晶硅层。 在形成之后并且在部分地限定第一多晶硅层之前，该工艺至少在浮栅存储晶体管的沟道区域处注入以调整晶体管阈值。
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7.发明授权Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method 有权具有其通过注入设定的阈值的EEPROM类型的存储单元以及制造方法公开(公告)号：US06268247B1
公开(公告)日：2001-07-31
申请号：US09431302
申请日：1999-10-29
IPC分类号： H01L218247
CPC分类号： H01L29/66825
摘要： A process forms a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of, in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer; depositing and partly defining a first polysilicon layer; forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor; depositing a second polysilicon layer; selectively etching away, through a first mask, at least the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor; and selectively etching away, through a second mask, the interpoly dielectric layer and the first polysilicon layer at the cell. After the selective etch through said second mask, an implantation step is only carried out through the second mask and at least at the channel region of the floating-gate storage transistor to set the transistor threshold.
摘要翻译： 一种工艺形成结合有至少一个电路晶体管和EEPROM型的至少一个非易失性存储单元的结构，其具有两个自对准多晶硅层，该层具有存储晶体管和相关选择晶体管，该半导体材料的衬底包括场氧化物区域 边界活跃区域。 该方法包括以下步骤：在有源区域中形成栅极氧化层并限定栅极氧化物层中包括的隧道氧化物区域; 沉积并部分地限定第一多晶硅层; 形成多余介电层，并至少在电路晶体管处除去多晶硅间介电层; 沉积第二多晶硅层; 通过第一掩模选择性地蚀刻在电池晶体管处的至少第二多晶硅层以及电路晶体管处的第一和第二多晶硅层; 并且通过第二掩模选择性地蚀刻在电池处的多晶硅间介电层和第一多晶硅层。 在通过所述第二掩模的选择性蚀刻之后，仅通过第二掩模并且至少在浮栅存储晶体管的沟道区域处执行注入步骤以设置晶体管阈值。
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8.发明授权EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process 有权包括具有通过植入调整的阈值电压的选择晶体管的EEPROM存储单元及相关的制造过程公开(公告)号：US06221717B1
公开(公告)日：2001-04-24
申请号：US09406879
申请日：1999-09-28
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11529 , H01L27/11543
摘要： Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.
摘要翻译： 一种用于制造包括至少一个电路晶体管和至少一个具有相对选择晶体管的非易失性EEPROM存储单元的集成结构的工艺，其包括在硅衬底上的至少第一阶段的生长和定义栅氧化层，第二 在所述栅极氧化物层中的隧道氧化物区域的定义阶段，在所述栅极氧化物层和所述隧道氧化物区域上沉积和限定第一多晶硅层的第三阶段，中间介电层的生长和定义的第四阶段 在所述第一多晶硅层上，在用于所述电路晶体管的区域中选择性蚀刻和去除所述电介质中间层的第五阶段，具有第一类型导电性的掺杂剂的第六级离子注入，以将所述掺杂剂引入 沟道区域以便调整其阈值电压，第七级沉积和第二级定义 所述集成结构上的多晶硅层，在用于所述存储单元的区域中选择性蚀刻和去除所述第二多晶硅层的第八级，以及用于所述电路晶体管的所述区域中的所述第一和第二多晶硅层，以形成所述电路晶体管 以及在所述存储单元的所述区域中选择性蚀刻和去除所述中间介电层和所述第一多晶硅层的第九阶段，其中在所述第五阶段期间，所述中间介电层也被蚀刻和去除， 形成所述选择晶体管的通道，因此所述第六级离子注入允许将所述掺杂剂引入所述沟道区，并因此增加所述选择晶体管的阈值电压。
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公开(公告)号：US06097057A
公开(公告)日：2000-08-01
申请号：US996921
申请日：1997-12-23
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.
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10.发明授权
公开(公告)号：US6080626A
公开(公告)日：2000-06-27
申请号：US996923
申请日：1997-12-23
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.
摘要翻译： 形成在具有第一导电类型的半导体材料基板上的EEPROM型存储单元包括具有第二导电类型的漏极区域，并且在包括薄隧道氧化物区域的栅极氧化物区域的一侧延伸。 存储单元还包括具有第二导电类型的电连续性区域，横向形成在薄隧道氧化物区域下方，并且部分地与漏极区域重叠。 通过以预定的倾斜角度的注入产生电连续性的区域。
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