公开(公告)号：US06734084B1

公开(公告)日：2004-05-11

申请号：US10603982

申请日：2003-06-26

申请人： Yoshihiko Nemoto ,  Masataka Hoshino ,  Hitoshi Yonemura

发明人： Yoshihiko Nemoto ,  Masataka Hoshino ,  Hitoshi Yonemura

IPC分类号： H01L21326

CPC分类号： H01L21/76898 ,  Y10S438/928 ,  Y10S438/977

摘要： A method for manufacturing a semiconductor device is capable of controlling amounts of protrusion of penetration electrodes (5) from a rear surface of a semiconductor substrate (4) in a easy and accurate manner. Recesses (7) are formed in a substrate proper (6) that has a semiconductor circuit (2) formed on one surface thereof, and an insulation film (8) is formed on an inner wall surface of each of the recesses (7). A conductive material is filled into the recesses (7) through the insulation films (8) to form embedded electrodes (15) that constitute the penetration electrodes (5). A rear side of the substrate proper (6) is re moved until one end face of each of the embedded electrodes (15) is exposed, thereby to form the penetration electrodes (5). The rear surface of the substrate proper (6) is anodized to form an anodic oxide film (9), which is then removed by etching to form the semiconductor substrate (4).

摘要翻译： 半导体器件的制造方法能够容易且准确地控制从半导体衬底（4）的后表面突出的穿透电极（5）的量。 凹部（7）形成在其一面形成有半导体电路（2）的基板（6）上，在各凹部（7）的内壁面上形成有绝缘膜（8）。 通过绝缘膜（8）将导电材料填充到凹部（7）中，以形成构成穿透电极（5）的嵌入式电极（15）。 衬底本体（6）的后侧被移动直到每个嵌入电极（15）的一个端面露出，从而形成穿透电极（5）。 衬底本体（6）的后表面被阳极化以形成阳极氧化膜（9），然后通过蚀刻去除以形成半导体衬底（4）。

公开(公告)号：US06673700B2

公开(公告)日：2004-01-06

申请号：US09895020

申请日：2001-06-30

申请人： Charles H. Dennison ,  Guy C. Wicker ,  Tyler A. Lowrey ,  Stephen J. Hudgens ,  Chien Chiang ,  Daniel Xu

发明人： Charles H. Dennison ,  Guy C. Wicker ,  Tyler A. Lowrey ,  Stephen J. Hudgens ,  Chien Chiang ,  Daniel Xu

IPC分类号： H01L21326

CPC分类号： H01L27/2463 ,  G11C13/0004 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.

摘要翻译： 一种方法，包括在小于衬底上的接触区域的整个部分上形成牺牲层，所述牺牲层具有限定在所述接触区域上的边缘的厚度，在所述间隔物上形成间隔层，所述隔离层符合形状 的第一牺牲层，使得间隔层包括邻近第一牺牲层边缘的接触区域上的边缘部分，去除牺牲层，同时将间隔物层的边缘部分保持在接触区域上方，形成介于第 接触区域，去除边缘部分，并且将可编程材料形成到以前由边缘部分占据的接触区域。 一种包括可编程材料体积，导体和设置在所述可编程材料体积与所述导体之间的电极的装置，所述电极在一端与所述可编程材料的体积相连接的接触区域，其中所述接触面积小于 一端的表面积。

公开(公告)号：US06329254B1

公开(公告)日：2001-12-11

申请号：US09431301

申请日：1999-10-29

申请人： Carlo Cremonesi ,  Bruno Vajana ,  Roberta Bottini ,  Giovanna Dalla Libera

发明人： Carlo Cremonesi ,  Bruno Vajana ,  Roberta Bottini ,  Giovanna Dalla Libera

IPC分类号： H01L21326

CPC分类号： H01L27/11521 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

摘要： A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

摘要翻译： 一种工艺形成了结合有至少一个电路晶体管和EEPROM型的至少一个非易失性存储单元的结构，其中两个自对准多晶硅层具有存储晶体管和相关选择晶体管，该半导体材料包括场氧化物区域 边界活跃区域。 该方法包括以下步骤：在有源区域中，形成栅极氧化物层并限定栅极氧化物层中包括的隧道氧化物区域，沉积并部分地限定形成多晶硅互连层的第一多晶硅层，并至少除去多晶硅绝缘层 在电路晶体管处沉积第二多晶硅层选择性地蚀刻掉电池处的第二多晶硅层，以及在电路晶体管处的第一和第二多晶硅层，并且选择性地蚀刻离开电池的多晶硅间介电层和第一多晶硅层。 在形成之后并且在部分地限定第一多晶硅层之前，该工艺至少在浮栅存储晶体管的沟道区域处注入以调整晶体管阈值。

公开(公告)号：US06214704B1

公开(公告)日：2001-04-10

申请号：US09404428

申请日：1999-09-23

申请人： Yun-Biao Xin

发明人： Yun-Biao Xin

IPC分类号： H01L21326

CPC分类号： H01L21/02013 ,  H01L21/02008 ,  H01L21/02024

摘要： A method of processing a semiconductor wafer sliced from a single-crystal ingot includes lapping front and back surfaces of the wafer to reduce the thickness of the wafer and to improve the flatness of the wafer. The front surface is subjected to fine grinding to reduce the damage on the front surface while leaving damage on the back surface intact. The front and back surfaces are simultaneously polished to improve the flatness of the wafer and to reduce wafer damage on the front and back surfaces. The wafer damage remaining on the back surface is greater than the wafer damage on the front surface. The wafer damage remaining on the back surface facilitates gettering.

摘要翻译： 处理从单晶锭切片的半导体晶片的方法包括研磨晶片的前表面和后表面以减小晶片的厚度并提高晶片的平坦度。 前表面进行细磨以减少前表面的损伤，同时在背面完好无损地损坏。 前表面和后表面被同时抛光以提高晶片的平整度并减少前表面和背面上的晶片损坏。 背面残留的晶片损伤大于前表面上的晶片损坏。 背面残留的晶片损伤有助于吸气。

公开(公告)号：US06362079B1

公开(公告)日：2002-03-26

申请号：US09341323

申请日：1999-07-09

申请人： Hitoshi Iwata ,  Makoto Murate

发明人： Hitoshi Iwata ,  Makoto Murate

IPC分类号： H01L21326

CPC分类号： H01L21/02203 ,  G01P15/0802 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/31675 ,  Y10S438/96 ,  Y10S438/962

摘要： A first p-type silicon layer (3) is formed as a buried layer in a p-type single crystal silicon substrate (2), and an n-type silicon layer (4) is formed on the upper side of the silicon substrate (2). A second p-type silicon layer (5) for forming an opening is defined in the n-type silicon layer (4), and a metal protecting film (14) is formed on the upper side of the n-type silicon layer (4). An electrode layer (18) is formed on the rear side of the silicon substrate (2) via an oxide film (17). The electrode layer (18) and the silicon substrate (2) are electrically connected to each other via a connecting opening (17a) at portions aligned with the first p-type silicon layer (3). After a positive terminal and a negative terminal of a DC power source (V) are connected to the electrode layer (18) and to a counter electrode (11) respectively, a voltage is applied between the electrode layer (18) and the counter electrode (11) to carry out anodization.

摘要翻译： 在p型单晶硅衬底（2）中形成第一p型硅层（3）作为掩埋层，并且在硅衬底的上侧形成n型硅层（4） 2）。 在n型硅层（4）中限定用于形成开口的第二p型硅层（5），在n型硅层（4）的上侧形成有金属保护膜（14） ）。 通过氧化膜（17）在硅衬底（2）的后侧形成电极层（18）。 电极层（18）和硅衬底（2）在与第一p型硅层（3）对准的部分处经由连接开口（17a）彼此电连接。 在直流电源（V）的正端子和负端子分别连接到电极层（18）和对电极（11）之后，在电极层（18）和对电极 （11）进行阳极氧化处理。

公开(公告)号：US06197664B1

公开(公告)日：2001-03-06

申请号：US09229503

申请日：1999-01-12

申请人： Michael G. Lee ,  Michael G. Peters ,  William T. Chou

发明人： Michael G. Lee ,  Michael G. Peters ,  William T. Chou

IPC分类号： H01L21326

CPC分类号： H05K3/423 ,  C25D7/123 ,  H05K3/427 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H05K2203/105

摘要： A method for plating conductive material in through apertures and blind apertures of a substrate which has a conductive material on its upper and lower surfaces. In a typical configuration for plating a via, there is a first region of conductive material adjacent to, but outside of, the aperture which forms the via and a second region of conductive material inside of the aperture. The second conductive region is selected to be the cathode of the plating process. The structure is placed in a plating bath, a first potential is applied to the first region of conductive material, and a second potential is applied to the second region of conductive material, with the second potential being different from the first potential. Under these conditions, material will plate onto the second region of conductive material to fill the aperture. The value of the first potential is preferably selected to substantially reduce the rate at which the first region of conductive material is etched by the plating bath, and may be used to cause material to be plated onto first region, but at a slower rate than the plating of the second conductive region.

摘要翻译： 一种用于在导电材料的上部和下部表面上具有导电材料的通孔和盲孔中的导电材料的电镀方法。 在用于电镀通孔的典型配置中，存在与形成通孔的孔相邻但在其外部的导电材料的第一区域，以及在孔内部的导电材料的第二区域。 选择第二导电区域作为电镀工艺的阴极。 将结构放置在电镀槽中，将第一电位施加到导电材料的第一区域，并且将第二电位施加到导电材料的第二区域，其中第二电位不同于第一电位。 在这些条件下，材料将镀在导电材料的第二区域上以填充孔。 优选地选择第一电位的值以显着降低电镀槽对导电材料的第一区域进行蚀刻的速率，并且可以用于使材料镀在第一区域上，但是以比 电镀第二导电区域。

公开(公告)号：US06171934B2

公开(公告)日：2001-01-09

申请号：US09144297

申请日：1998-08-31

申请人： Vikram Joshi ,  Narayan Solayappan ,  Walter Hartner ,  G{umlaut over (u)}nther Schindler

发明人： Vikram Joshi ,  Narayan Solayappan ,  Walter Hartner ,  G{umlaut over (u)}nther Schindler

IPC分类号： H01L21326

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal. The voltage-cycling recovery process obviates oxygen-recovery annealing, and it allows continued use of conventional hydrogen-rich plasma processes and forming-gas anneals without the risk of permanent damage to the ferroelectric thin film.

摘要翻译： 形成含有金属氧化物铁电体薄膜的集成电路。 进行电压循环恢复处理以逆转由氢引起的铁电性能的降低。 通过施加电压幅度为1至15伏特的104至1011个电压周期来执行电压循环恢复过程。 在30-200℃范围内的较高温度下进行电压循环，提高了回收率。 优选地，金属氧化物薄膜包括层状超晶格材料。 优选地，层状超晶格材料包括钽酸铋钽铋或铌酸铋钽酸铋。 如果集成电路制造包括成形气体退火，则在成形气体退火之后执行电压循环恢复过程。 电压循环恢复过程避免氧回收退火，并且其允许继续使用常规富氢等离子体工艺和形成气体退火，而不会对铁电薄膜造成永久损坏的风险。

公开(公告)号：US06524934B1

公开(公告)日：2003-02-25

申请号：US09429224

申请日：1999-10-28

申请人： D'Arcy H. Lorimer

发明人： D'Arcy H. Lorimer

IPC分类号： H01L21326

CPC分类号： B01J19/2485 ,  B01J12/007 ,  B01J19/002 ,  B01J2219/00135 ,  B01J2219/00263 ,  C01B5/00

摘要： The present invention increases the safety of a reactor for generating water vapor from oxygen and hydrogen, provides ultra-pure water vapor in an amount necessary for practical use safely, stably and continuously, provides ultra-pure water vapor concentrations to nearly 100 percent without the need of an inert transporting gas, and provides a catalyst with long term, high catalytic activity within the reactor. Specifically, the system comprises a catalyst vessel and a plurality of sorption vessels. The catalyst vessel is made of a heat-resistant material and includes an inlet and an outlet for water vapor and inert gas mixture, a heat source, and has a platinum or palladium catalyst within the catalyst vessel. The sorption vessels are made of a heat-resistant material and includes an inlet and an outlet for water vapor and inert gas mixture, a heat source, and has a molecular sieve water vapor sorption material within the sorption vessel. Hydrogen, oxygen and an inert gas fed from the inlet of the reactor vessel contacts the catalyst to enhance reactivity, thereby producing water from hydrogen and oxygen. The water vapor and inert gas mixture flows from the reactor vessel to the sorption vessel, where the water vapor and inert gas mixture contacts the sorption material. The sorption material sorbs the water vapor from the water vapor and inert gas mixture. The inert gas is exhausted. Then, the water vapor and inert gas mixture flowing from the reactor vessel to the sorption vessel is stopped. Then, the sorption vessel heated to release ultra-pure water vapor. A temperature of the sorption material determines the flowrate of the water vapor from the system.

摘要翻译： 本发明增加了用于从氧气和氢气产生水蒸汽的反应器的安全性，提供了实际使用所需量的超纯水蒸气，其安全，稳定和连续地提供超纯水蒸汽浓度达到近100％ 需要惰性输送气体，并且在反应器内提供具有长期，高催化活性的催化剂。 具体地，该系统包括催化剂容器和多个吸附容器。 催化剂容器由耐热材料制成，并且包括用于水蒸气和惰性气体混合物的入口和出口，热源，并且在催化剂容器内具有铂或钯催化剂。 吸附容器由耐热材料制成，并且包括用于水蒸气和惰性气体混合物的入口和出口，热源，并且在吸附容器内具有分子筛水蒸气吸附材料。 从反应器容器的入口供给的氢气，氧气和惰性气体与催化剂接触以提高反应活性，由此产生氢气和氧气。 水蒸汽和惰性气体混合物从反应器容器流到吸附容器，其中水蒸汽和惰性气体混合物接触吸附材料。 吸附材料吸收水蒸气和惰性气体混合物中的水蒸气。 惰性气体耗尽。 然后，停止从反应器容器流到吸附容器的水蒸汽和惰性气体混合物。 然后，吸附容器被加热以释放超纯水蒸汽。 吸附材料的温度决定了来自系统的水蒸汽的流量。

公开(公告)号：US06444544B1

公开(公告)日：2002-09-03

申请号：US09629940

申请日：2000-08-01

申请人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

发明人： Chu-Wei Hu ,  Chung-Te Lin ,  Kuo-Hua Pan ,  Hsien-Chin Lin

IPC分类号： H01L21326

CPC分类号： H01L23/5258 ,  H01L23/53228 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

摘要翻译： 已经开发了一种在铜互连结构中形成用于保护铜互连结构免受激光写入过程的铝保护结构的方法，该方法对相邻的铜熔丝元件执行。 该方法的特征是在铜互连结构的上层形成保护结构开口，在铜熔丝元件的邻近区域。 铝层的沉积和图案化导致位于防护结构开口中的铝防护结构的形成。 铝保护结构保护铜互连结构免受在激光写入过程中产生的氧，氟和水离子对相邻铜熔丝元件的氧化和腐蚀作用。

公开(公告)号：US06323111B1

公开(公告)日：2001-11-27

申请号：US09428689

申请日：1999-10-28

申请人： Frank Y. Hui ,  Edward B. Harris

发明人： Frank Y. Hui ,  Edward B. Harris

IPC分类号： H01L21326

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.

摘要翻译： 用于集成电路的保险丝包括介电层，由顶部开口和底部底部限定沟槽或空隙。 沟槽包括至少一个底切部，该底切部在屏蔽底层的介电层中形成伸出部。 沉积在电介质层上的第二或阻挡层在底切处被中断或不连续。 第三个或导电层在保险丝上电连续。 第三层的弱点存在于中断时第二层缺乏结构支撑。 在中断时，在导电层的电隔离中存在第三层中的另一个弱点，即没有通过阻挡层的泄漏电流。