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1.发明授权Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique 有权通过非接触充电技术确定半导体/氧化物界面的阱密度的方法公开(公告)号：US06391668B1
公开(公告)日：2002-05-21
申请号：US09562346
申请日：2000-05-01
IPC分类号： H01L2166
CPC分类号： H01L22/14
摘要： The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.
摘要翻译： 本发明提供一种确定半导体衬底/电介质界面的阱密度的方法。 在一个实施例中，该方法包括测量由位于接口附近的陷阱的载流子导致的半导体衬底内的电流，其中测量的电流是位于界面处的陷阱的数量的函数，并且将陷阱密度确定为 测量电流的函数。
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公开(公告)号：US06605529B2
公开(公告)日：2003-08-12
申请号：US09853317
申请日：2001-05-11
申请人： Sundar Chetlur , Jennifer M. McKinley , Minesh A. Patel , Pradip K. Roy , Jonathan Zhong-Ning Zhou
发明人： Sundar Chetlur , Jennifer M. McKinley , Minesh A. Patel , Pradip K. Roy , Jonathan Zhong-Ning Zhou
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28035 , H01L21/28176 , H01L21/28211 , H01L21/3003 , H01L29/4925 , H01L29/51 , H01L29/513
摘要： The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.
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