公开(公告)号：US07906815B2

公开(公告)日：2011-03-15

申请号：US12056362

申请日：2008-03-27

申请人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

发明人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

摘要翻译： 通过形成直接接触结构，例如通过在硅化处理之前去除侧壁间隔物，在增加量的金属硅化物的基础上连接有源区域，可以在接触期间实现显着增加的蚀刻选择性 蚀刻停止层开口。 因此，有效区域的高掺杂硅材料的过度蚀刻将被抑制。 附加地或替代地，公开了适当设计的测试结构，其可以检测根据特定制造顺序形成的接触结构的电特性，并且可以基于特定的设计标准。

公开(公告)号：US07998823B2

公开(公告)日：2011-08-16

申请号：US11533793

申请日：2006-09-21

申请人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

发明人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

IPC分类号： H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/76897 ,  H01L21/823475

摘要： By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

摘要翻译： 通过在接触区域可以连接到漏极和源极区域的区域处形成具有增加的结深度的附加掺杂区域，可以将任何接触不规则物嵌入到附加掺杂区域中，从而降低漏极和漏极之间的漏电流或短路的风险 源极区域和通常由接触不规则引起的阱区域。 此外，附加地或替代地，可以在形成金属硅化物区域和接触插塞之前修改半导体区域和相邻隔离沟槽的表面形貌，以增强在层间电介质材料中形成相应接触开口的光刻过程。 为此，与相邻的半导体区域相比，隔离沟槽可以达到相同或更高的水平。

公开(公告)号：US20090085030A1

公开(公告)日：2009-04-02

申请号：US12056362

申请日：2008-03-27

申请人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

发明人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

IPC分类号： H01L29/06 ,  H01L21/44 ,  H01L29/78

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

摘要翻译： 通过形成直接接触结构，例如通过在硅化处理之前去除侧壁间隔物，在增加量的金属硅化物的基础上连接有源区域，可以在接触期间实现显着增加的蚀刻选择性 蚀刻停止层开口。 因此，有效区域的高掺杂硅材料的过度蚀刻将被抑制。 附加地或替代地，公开了适当设计的测试结构，其可以检测根据特定制造顺序形成的接触结构的电特性，并且可以基于特定的设计标准。

公开(公告)号：US20070161225A1

公开(公告)日：2007-07-12

申请号：US11533793

申请日：2006-09-21

申请人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

发明人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823481 ,  H01L21/76897 ,  H01L21/823475

摘要： By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

摘要翻译： 通过在接触区域可以连接到漏极和源极区域的区域处形成具有增加的结深度的附加掺杂区域，可以将任何接触不规则物嵌入到附加掺杂区域中，从而降低漏极和漏极之间的漏电流或短路的风险 源极区域和通常由接触不规则引起的阱区域。 此外，附加地或替代地，可以在形成金属硅化物区域和接触插塞之前修改半导体区域和相邻隔离沟槽的表面形貌，以增强在层间电介质材料中形成相应接触开口的光刻过程。 为此，与相邻的半导体区域相比，隔离沟槽可以达到相同或更高的水平。

公开(公告)号：US20110210447A1

公开(公告)日：2011-09-01

申请号：US12939523

申请日：2010-11-04

申请人： Robert Seidel ,  Kai Frohberg ,  Carsten Peters

发明人： Robert Seidel ,  Kai Frohberg ,  Carsten Peters

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76814 ,  H01L21/76829 ,  H01L29/66795 ,  H01L2029/7858

摘要： In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer.

摘要翻译： 在复杂的半导体器件中，可以通过图案化接触开口并以公共沉积顺序用第一金属化层的金属填充接触开口来形成接触电平的接触元件。 为此，在一些说明性实施例中，在沉积第一金属化层的介电材料之前，可以在接触开口中提供牺牲填充材料。

公开(公告)号：US20080131257A1

公开(公告)日：2008-06-05

申请号：US11756124

申请日：2007-05-31

申请人： Carsten Peters ,  Thomas Werner ,  Frank Feustel ,  Kai Frohberg

发明人： Carsten Peters ,  Thomas Werner ,  Frank Feustel ,  Kai Frohberg

IPC分类号： B65H1/00 ,  B05D5/10 ,  G06F19/00 ,  B65B33/00

CPC分类号： H01L21/67346

摘要： By providing a safety material, such as an adhesive foil, the probability for transport-related damage or destruction of substrates caused by broken substrates may be significantly reduced.

摘要翻译： 通过提供诸如粘合箔的安全材料，可能会显着降低由于破碎的基材导致的与基板相关的损坏或破坏基板的可能性。

公开(公告)号：US20070099414A1

公开(公告)日：2007-05-03

申请号：US11428611

申请日：2006-07-05

申请人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

发明人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive material such as copper or a copper alloy, a significant increase in conductivity of the contact structure may be achieved. For this purpose, after the deposition of a first dielectric layer of the inter-layer stack, a planarization process may be performed so as to allow the formation of the lower plug portions on the basis of tungsten, while, after the deposition of the second dielectric layer, a corresponding copper-based technology may be used for forming the upper plug portions of significantly enhanced conductivity.

摘要翻译： 通过提供具有基于已经确定的钨基技术形成的下部插塞部分的接触插塞和可包括诸如铜或铜合金的高导电材料的上部插塞部分，导电性的显着增加 可以实现接触结构。 为此，在沉积层间堆叠的第一介电层之后，可以进行平面化处理，以便允许基于钨形成下部塞子部分，而在沉积第二层 电介质层，可以使用相应的铜基技术来形成具有显着增强的导电性的上部插塞部分。

公开(公告)号：US07902581B2

公开(公告)日：2011-03-08

申请号：US11428611

申请日：2006-07-05

申请人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

发明人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive material such as copper or a copper alloy, a significant increase in conductivity of the contact structure may be achieved. For this purpose, after the deposition of a first dielectric layer of the inter-layer stack, a planarization process may be performed so as to allow the formation of the lower plug portions on the basis of tungsten, while, after the deposition of the second dielectric layer, a corresponding copper-based technology may be used for forming the upper plug portions of significantly enhanced conductivity.

摘要翻译： 通过提供具有基于已经确定的钨基技术形成的下部插塞部分的接触插塞和可包括诸如铜或铜合金的高导电材料的上部插塞部分，导电性的显着增加 可以实现接触结构。 为此，在沉积层间堆叠的第一介电层之后，可以进行平面化处理，以便允许基于钨形成下部塞子部分，而在沉积第二层 电介质层，可以使用相应的铜基技术来形成具有显着增强的导电性的上部插塞部分。

公开(公告)号：US20090108462A1

公开(公告)日：2009-04-30

申请号：US12104692

申请日：2008-04-17

申请人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

发明人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density.

摘要翻译： 通过在电阻敏感的金属化层中形成延伸穿过整个层间电介质材料的金属线，可获得这些金属化层的均匀性。 相应过孔开口的图案化可以基于形成在盖层中的凹槽来实现，该凹槽在沟槽图案化期间另外充当有效的蚀刻停止层，其延伸穿过整个层间电介质材料。 因此，对于电阻敏感金属化层中金属线的给定设计宽度，可以获得具有高程度均匀性的金属线的最大横截面积，而与通孔密度的变化无关。

公开(公告)号：US07482219B2

公开(公告)日：2009-01-27

申请号：US11424272

申请日：2006-06-15

申请人： Kai Frohberg ,  Carsten Peters ,  Matthias Schaller ,  Heike Salz

发明人： Kai Frohberg ,  Carsten Peters ,  Matthias Schaller ,  Heike Salz

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76831 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a technique for forming differently stressed contact etch stop layers, wherein sidewall spacers are removed prior to the formation of the contact etch stop layers. During the partial removal of respective contact etch stop layers, a corresponding etch stop layer regime is used to substantially avoid any unwanted stress-inducing material residuals, thereby significantly enhancing the stress transfer mechanism.

摘要翻译： 本发明提供了形成不同应力的接触蚀刻停止层的技术，其中在形成接触蚀刻停止层之前去除侧壁间隔物。 在部分去除相应的接触蚀刻停止层期间，使用相应的蚀刻停止层状态来基本上避免任何不需要的应力诱导材料残余物，从而显着增强应力传递机制。