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公开(公告)号:US20170338142A1
公开(公告)日:2017-11-23
申请号:US15670364
申请日:2017-08-07
Applicant: Cascade Microtech, Inc.
Inventor: Michael E. Simmons , Kazuki Negishi , Ryan Garrison , Philip Wolf
IPC: H01L21/683 , G01R31/28
CPC classification number: H01L21/6838 , G01R31/2601 , G01R31/2865 , G01R31/2874 , Y10T279/11 , Y10T279/34
Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.
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公开(公告)号:US09741599B2
公开(公告)日:2017-08-22
申请号:US15072170
申请日:2016-03-16
Applicant: Cascade Microtech, Inc.
Inventor: Michael E. Simmons , Kazuki Negishi , Ryan Garrison , Philip Wolf
IPC: H01L21/683 , G01R31/26 , G01R31/28
CPC classification number: H01L21/6838 , G01R31/2601 , G01R31/2865 , G01R31/2874 , Y10T279/11 , Y10T279/34
Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.
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公开(公告)号:US20160195579A1
公开(公告)日:2016-07-07
申请号:US15072170
申请日:2016-03-16
Applicant: Cascade Microtech, Inc.
Inventor: Michael E. Simmons , Kazuki Negishi , Ryan Garrison , Philip Wolf
IPC: G01R31/26 , H01L21/683
CPC classification number: H01L21/6838 , G01R31/2601 , G01R31/2865 , G01R31/2874 , Y10T279/11 , Y10T279/34
Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.
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公开(公告)号:US10062597B2
公开(公告)日:2018-08-28
申请号:US15670364
申请日:2017-08-07
Applicant: Cascade Microtech, Inc.
Inventor: Michael E. Simmons , Kazuki Negishi , Ryan Garrison , Philip Wolf
IPC: H01L21/683 , G01R31/28
Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.
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公开(公告)号:US09991152B2
公开(公告)日:2018-06-05
申请号:US14631131
申请日:2015-02-25
Applicant: CASCADE MICROTECH, INC.
Inventor: Robbie Ingram-Goble , Michael E. Simmons , Philip Wolf , Ryan Garrison , Christopher Storm
IPC: H01L21/683 , B25J15/06 , B25J11/00 , B25J15/00 , H01L21/677
CPC classification number: H01L21/6838 , B25J11/0095 , B25J15/0014 , B25J15/0616 , H01L21/67778 , Y10S901/40
Abstract: Wafer-handling end effectors and semiconductor manufacturing devices that include and/or are utilized with wafer-handling end effectors are disclosed herein. The end effectors include an end effector body and a plurality of wafer-contacting surfaces that is supported by the end effector body and configured to form an at least partially face-to-face contact with a wafer. The end effectors further include a vacuum distribution manifold that extends between a robot-proximal end of the end effector body and the plurality of wafer-contacting surfaces. The end effectors also include a plurality of vacuum openings that is defined within the plurality of wafer-contacting surfaces and extends between the plurality of wafer-contacting surfaces and the vacuum distribution manifold. The end effectors further include a plurality of sealing structures each of which is associated with a respective one of the plurality of wafer-contacting surfaces.
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公开(公告)号:US20150255322A1
公开(公告)日:2015-09-10
申请号:US14631131
申请日:2015-02-25
Applicant: CASCADE MICROTECH, INC.
Inventor: Robbie Ingram-Goble , Michael E. Simmons , Philip Wolf , Ryan Garrison , Christopher Storm
IPC: H01L21/683 , B25J11/00 , B25J15/06
CPC classification number: H01L21/6838 , B25J11/0095 , B25J15/0014 , B25J15/0616 , H01L21/67778 , Y10S901/40
Abstract: Wafer-handling end effectors and semiconductor manufacturing devices that include and/or are utilized with wafer-handling end effectors are disclosed herein. The end effectors include an end effector body and a plurality of wafer-contacting surfaces that is supported by the end effector body and configured to form an at least partially face-to-face contact with a wafer. The end effectors further include a vacuum distribution manifold that extends between a robot-proximal end of the end effector body and the plurality of wafer-contacting surfaces. The end effectors also include a plurality of vacuum openings that is defined within the plurality of wafer-contacting surfaces and extends between the plurality of wafer-contacting surfaces and the vacuum distribution manifold. The end effectors further include a plurality of sealing structures each of which is associated with a respective one of the plurality of wafer-contacting surfaces.
Abstract translation: 本文公开了包括和/或与晶片处理端效应器一起使用的晶片处理末端执行器和半导体制造装置。 末端执行器包括末端执行器主体和多个晶片接触表面,其由端部执行器主体支撑并被配置为与晶片形成至少部分的面对面的接触。 末端执行器还包括在末端执行器主体的机器人近端与多个晶片接触表面之间延伸的真空分配歧管。 末端执行器还包括限定在多个晶片接触表面内并在多个晶片接触表面和真空分配歧管之间延伸的多个真空开口。 末端执行器还包括多个密封结构,每个密封结构与多个晶片接触表面中的相应一个相关联。
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