公开(公告)号：US5212413A

公开(公告)日：1993-05-18

申请号：US726470

申请日：1991-07-08

申请人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

发明人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

IPC分类号： H03K19/173 ,  G11C29/04 ,  H03K3/356

CPC分类号： H03K3/356008

摘要： When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

公开(公告)号：US5265064A

公开(公告)日：1993-11-23

申请号：US449666

申请日：1989-12-12

申请人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： G11C11/41 ,  H03K3/033 ,  H03K3/78 ,  H03K5/04 ,  H03K5/156 ,  G11C8/00

CPC分类号： H03K5/04 ,  H03K3/033 ,  H03K5/156

摘要： A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3). The circuit may be used as an equalisation pulse generator for a data path in a semiconductor memory integrated circuit.

公开(公告)号：US5912529A

公开(公告)日：1999-06-15

申请号：US826915

申请日：1997-04-09

申请人： Hendrik J. De Wit, deceased ,  Henricus J. Kunnen, legal representative

发明人： Hendrik J. De Wit, deceased ,  Henricus J. Kunnen, legal representative

IPC分类号： G06F1/16 ,  H04N5/65 ,  H04N9/29 ,  H01J29/80

CPC分类号： H04N5/65 ,  G06F1/1601 ,  H04N9/29 ,  G06F2200/1611

摘要： A display device comprising a display tube having a display screen with a pattern of phosphor elements. To reduce mislandings of electron beams, the display tube is accommodated within an external magnetic shield which is formed by one or more individual frames composed of bars of a magnetizable material and one or more excitable coils. The coils may be arranged, for example, alongside the frames.

摘要翻译： 一种显示装置，包括具有荧光体元件图案的显示屏的显示管。 为了减少电子束的误放，显示管容纳在由可磁化材料的条和一个或多个可激发线圈组成的一个或多个单独的框架形成的外部磁屏蔽内。 线圈可以例如与框架一起布置。