公开(公告)号：US5212413A

公开(公告)日：1993-05-18

申请号：US726470

申请日：1991-07-08

申请人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

发明人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

IPC分类号： H03K19/173 ,  G11C29/04 ,  H03K3/356

CPC分类号： H03K3/356008

摘要： When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

公开(公告)号：US5265064A

公开(公告)日：1993-11-23

申请号：US449666

申请日：1989-12-12

申请人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： G11C11/41 ,  H03K3/033 ,  H03K3/78 ,  H03K5/04 ,  H03K5/156 ,  G11C8/00

CPC分类号： H03K5/04 ,  H03K3/033 ,  H03K5/156

摘要： A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3). The circuit may be used as an equalisation pulse generator for a data path in a semiconductor memory integrated circuit.

公开(公告)号：US4929911A

公开(公告)日：1990-05-29

申请号：US296462

申请日：1989-05-22

申请人： Thomas J. Davies ,  Evert Seevinck ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kennen ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Evert Seevinck ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kennen ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： H03K19/0185 ,  H03K17/687 ,  H03K19/003

CPC分类号： H03K19/00315

摘要： A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

公开(公告)号：US5224071A

公开(公告)日：1993-06-29

申请号：US390326

申请日：1989-08-07

申请人： Cormac O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Cormac O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C11/41 ,  G11C8/06

CPC分类号： G11C8/06

摘要： An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.

摘要翻译： 可寻址存储器单元具有地址输入缓冲器电路，其输出一对输出连接，在读出或写入模式中，存在彼此互补的两个信号，但是也可以以这样的方式采用相等的值， 预解码器和线选择器来选择所有或没有选择线来控制所访问的存储器的单元。

公开(公告)号：US4951254A

公开(公告)日：1990-08-21

申请号：US272180

申请日：1988-11-16

申请人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

发明人： Hans Ontrop ,  Roelof Salters ,  Betty Prince ,  Thomas J. Davies ,  Cathal G. Phelan ,  Cormac O'Connell ,  Peter H. Voss ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. by Kunnen, legal representative

IPC分类号： G11C29/00 ,  G01R31/317 ,  G06F11/00 ,  G06F11/22 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46

CPC分类号： G06F11/2273 ,  G01R31/31701 ,  G06F11/006 ,  G11C29/46

摘要： Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

摘要翻译： 具有多个测试模式的随机存取存储器单元，其被构造为集成电路，并且不包括特定的输入/输出引脚来定义和命令通过测试模式。 该单元配备有用于检测在通常使用的一组序列内但是其电压是否包括在指定的电压范围内的未包含的预定义逻辑信号序列的装置（1） 对于这样的信号，被提供给某些输入（CE，WE，AO），并且当检测到这样的序列时，将单元置于测试模式。 为了定义要执行的测试的性质，单元的地址输入端（A1-A8）连接到测试模式解码电路（2），其中将施加到所述输入端的数据用作 定义要执行的测试的性质的数据。

公开(公告)号：US5229709A

公开(公告)日：1993-07-20

申请号：US971708

申请日：1992-11-04

申请人： Leonardus C. M. G. Pfennings, deceased

发明人： Leonardus C. M. G. Pfennings, deceased

IPC分类号： G05F1/625

CPC分类号： G05F1/625 ,  Y10S323/907

摘要： An integrated circuit has an internal supply voltage with a positive temperature coefficient, as a result of which the switching rate and the degree of "hot carrier stress" are less sensitive to temperature. By using a reference voltage source having positive temperature coefficient, the normal effects of increasing temperature on switching rate and "hot carrier stress" are compensated for, thus stabilizing circuit operation as a function of temperature. The reference voltage source is incorporated within a voltage converter which is already present in the circuit, to achieve a compact and efficient configuration.

摘要翻译： 集成电路具有正温度系数的内部电源电压，因此开关速率和“热载流子应力”的程度对温度较不敏感。 通过使用具有正温度系数的参考电压源，补偿温度升高对开关速率和“热载流子应力”的正常影响，从而稳定电路作为温度的函数。 参考电压源被并入已经存在于电路中的电压转换器中，以实现紧凑而有效的配置。