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    Array redundancy supporting multiple independent repairs
    1.
    发明授权
    Array redundancy supporting multiple independent repairs 失效
    支持多个独立维修的阵列冗余

    公开(公告)号：US07206236B1

    公开(公告)日：2007-04-17

    申请号：US11330693

    申请日：2006-01-12

    申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Elizabeth Lair Gerhard ,  George Francis Paulik

    发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Elizabeth Lair Gerhard ,  George Francis Paulik

    IPC分类号： G11C29/00

    CPC分类号： G11C29/848

    摘要： Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.

    摘要翻译： 使用冗余位线修复具有多个独立故障的诸如SRAM，DRAM，CAM和可编程ROM的阵列。 第一实施例在阵列的一侧提供冗余位线。 在写入期间，数据将朝着阵列一侧的冗余位线移动，绕过故障位线。 第二实施例在阵列的每一侧提供备用位线。 在写入期间，第一故障位线由阵列的第一侧上的第一备用位线替代，并且第二故障位线被阵列的第二侧上的第二备用位线替代。

    Method and ring oscillator for evaluating dynamic circuits
    2.
    发明授权
    Method and ring oscillator for evaluating dynamic circuits 有权
    用于评估动态电路的方法和环形振荡器

    公开(公告)号：US06538522B1

    公开(公告)日：2003-03-25

    申请号：US09977423

    申请日：2001-10-15

    申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  David Michael Friend ,  Nghia Van Phan

    发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  David Michael Friend ,  Nghia Van Phan

    IPC分类号： H03B2700

    CPC分类号： H03K3/0315

    摘要： Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit. The multiplexer receives the pulse output of the one-shot pulse generator and includes a select input for selecting the output of the dynamic circuit to be evaluated or the pulse output of the one-shot pulse generator. By inserting the evaluation circuit into a path that can be multiplexed in and out of the oscillator path, and by measuring the difference between the frequency with and without the evaluation circuit in the path, the performance of the evaluation circuit can be accurately determined.

    摘要翻译： 提供测量方法和环形振荡器电路用于评估动态电路。 环形振荡器电路包括接收单个转换输入信号的单触发脉冲发生器，并产生具有上升的转换和下降转换的脉冲输出信号。 要评估的动态电路耦合到接收单触发脉冲发生器的脉冲输出信号的单触发脉冲发生器的输出，并在输出端产生延迟的输出脉冲。 二分之一电路耦合到待评估的动态电路的输出。 二分之一电路的输出信号反馈给单触发脉冲发生器，重复循环，从而振荡。 多路复用器连接在待评估的动态电路的输出端与分频电路之间。 复用器接收单触发脉冲发生器的脉冲输出，并且包括用于选择要评估的动态电路的输出或单触发脉冲发生器的脉冲输出的选择输入。 通过将评估电路插入到可以复用在振荡器路径中的路径之外，并且通过测量路径中具有和不具有评估电路的频率之间的差异，可以准确地确定评估电路的性能。

    Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme
    3.
    发明授权
    Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme 失效
    用于处理串行共享静态方案中可变数据字宽和阵列深度的方法和装置

    公开(公告)号：US5835502A

    公开(公告)日：1998-11-10

    申请号：US673258

    申请日：1996-06-28

    申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Murali Vaddigiri ,  Paul Wong

    发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Murali Vaddigiri ,  Paul Wong

    IPC分类号： G06F12/16 ,  G06F11/22 ,  G11C29/02 ,  G11C29/12 ,  G11C29/32 ,  G06F11/00

    CPC分类号： G11C29/32

    摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.

    摘要翻译： 一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。 每个阵列包括预定的行和列地址深度和数据字宽度。 每个阵列还包括扫描寄存器。 生成通用测试数据字并将其发送到每个阵列的扫描寄存器。 通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。 超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。

    Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test
    5.
    发明授权
    Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test 有权
    使用位线预充电应力操作来对存储单元进行测试的硅绝缘体SRAM存储单元的稳定性测试

    公开(公告)号：US06643804B1

    公开(公告)日：2003-11-04

    申请号：US09552410

    申请日：2000-04-19

    申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

    发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

    IPC分类号： G11C2900

    CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C2029/1204

    摘要： An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell during testing to stress the memory cell such that a reliable determination of stability may be made. Stress is applied to a memory cell through the use of a bitline precharge stress operation, which utilizes the bitline pairs coupled to a memory cell to attempt to flood the memory cell with charge and thereby attempt to cause the memory cell to unexpectedly switch state. The bitline precharge stress operation is performed immediately after the memory cell has been switched to one state after being maintained in an opposite state for a length of time that is sufficient to introduce switching history effects to the memory cell. While a bitline precharge operation may be implemented separate from any write operation, the bitline precharge stress operation may also be incorporated into a write operation through delaying the deassertion of the wordline that occurs in a conventional write operation until after initiation of the bitline precharge operation that conventionally occurs near the end of such a write operation.

    摘要翻译： 一种测试绝缘体上硅（SOI）静态随机存取存储器（SRAM）的装置，程序产品和方法在测试期间向存储器单元引入开关历史效应以对存储单元施加压力，从而稳定性的可靠确定可以是 制作。 通过使用位线预充电应力操作将应力施加到存储器单元，其利用耦合到存储器单元的位线对尝试以充电方式溢出存储器单元，从而尝试使存储器单元意外地切换状态。 在将存储单元切换到一个状态之后，立即执行位线预充电应力操作，并将其保持在相反的状态，持续足以将切换历史效应引入存储单元的时间长度。 尽管位线预充电操作可以与任何写操作分开实施，但是位线预充电应力操作也可以通过延迟在常规写操作中发生的字线的取消取消而被并入到写操作中，直到在开始位线预充电操作之后， 通常在这种写入操作的结束附近发生。

    Split local and continuous bitline for fast domino read SRAM
    8.
    发明授权
    Split local and continuous bitline for fast domino read SRAM 有权
    分割本地和连续的位线快速多米诺骨牌SRAM

    公开(公告)号：US06657886B1

    公开(公告)日：2003-12-02

    申请号：US10140549

    申请日：2002-05-07

    申请人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger

    发明人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger

    IPC分类号： G11C1140

    CPC分类号： G11C11/419

    摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.

    摘要翻译： 提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。 多米诺SRAM包括多个本地小区组。 多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。 连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。 要写入SRAM单元补码节点，只需要驱动连续的补码位线。 与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。

    High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus
    10.
    发明授权
    High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus 有权
    高性能，低电池应力，低功耗，SOI CMOS闩锁型感测方法和装置

    公开(公告)号：US06404686B1

    公开(公告)日：2002-06-11

    申请号：US09770912

    申请日：2001-01-26

    申请人： Anthony Gus Aipperspach ,  Fariborz Assaderaghi ,  Todd Alan Christensen ,  Douglas Michael Dewanz ,  Jente Benedict Kuang

    发明人： Anthony Gus Aipperspach ,  Fariborz Assaderaghi ,  Todd Alan Christensen ,  Douglas Michael Dewanz ,  Jente Benedict Kuang

    IPC分类号： G11C700

    CPC分类号： G11C7/065

    摘要： A high performance, low cell stress, low-power silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary bit and data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. The reduced bit and data line precharge voltage substantially reduces voltage stress applied to the access transistors in the RAM cells. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the. sense amplifier is set. The pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) field effect transistor (FET) in the sense amplifier. The pre-amplifying mechanism aids offset voltage development before the sense amplifier is set. The full rail voltage is provided for the complementary data lines when the sense amplifier is set. The full rail voltage can be applied during the write mode.

    摘要翻译： 提供了高性能，低电池应力，低功率绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）闩锁型感测方法和装置。 绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）锁存型读出放大器包括预充电电路，用于在预充电循环期间将互补位和数据线充电至预定的预充电电压。 预充电电压低于全路电压。 减小的位和数据线预充电电压基本上减小施加到RAM单元中的存取晶体管的电压。 预放大机制在之前的互补数据线之间产生偏移电压。 读出放大器设置。 该预放大机构包括一个预放大FET，该预放大FET基本上小于感测放大器中的感测绝缘体上（SOI）场效应晶体管（FET）。 预放大机制有助于在读出放大器设置之前的偏移电压发展。 当设置读出放大器时，为互补数据线提供全路电压。 在写入模式期间可以应用全路电压。